Single-Carrier Hybrid Switching Tames Voltage Noise in Three-Level Inverters

Engineers have long faced an awkward trade-off at the heart of modern power electronics: the switching strategies that keep a converter’s output current clean are the same ones that inflate its common-mode voltage, a hidden electrical nuisance that stresses motor insulation, drives bearing currents and complicates electromagnetic filtering. Now a research team reports a hybrid switching mechanism that breaks this compromise for three-phase, three-level T-type inverters, cutting common-mode voltage by roughly 22 percent compared with a conventional high-quality modulation scheme while keeping current distortion close to that same benchmark. The work, validated in both simulation and on a hardware prototype, achieves the result with a single carrier signal and a simple polarity test, adding almost no computational burden to the controller.

The T-type inverter at the center of the study belongs to the neutral-point-clamped family. Each of its three phase legs contains four switching devices, and a mid-point formed by two series DC-link capacitors allows the output to take three discrete voltage levels: negative half the DC-link voltage, zero, and positive half. Compared with ordinary two-level inverters, this three-level structure reduces voltage stress on the semiconductors, lowers switching losses and produces a markedly better harmonic profile, which is why the topology has become attractive for renewable energy systems, medium-voltage motor drives and industrial converters where efficiency, power quality and thermal management all matter simultaneously.

Yet the topology brings its own headaches. Selecting among the many available voltage vectors and managing their switching states is more complex than in a two-level converter, and poor choices show up as common-mode voltage fluctuations, excessive total harmonic distortion and degraded dynamic response under load disturbances. The common-mode voltage itself arises directly from the switching pattern: it equals one-sixth of the DC-link voltage multiplied by the algebraic sum of the three leg levels. Because each leg can sit at minus one, zero or plus one in normalized terms, that sum spans seven discrete values, from minus three to plus three, corresponding to common-mode excursions between minus and plus half the DC-link voltage. The zero vectors, in which all three legs sit at the same level, produce the worst case.

This geometric fact underpins the entire new strategy. Suppressing common-mode voltage, the researchers explain, is equivalent to excluding from the reachable set those switching triplets whose level sum is large. A modulator confined to triplets whose sum never exceeds one in magnitude keeps the common-mode voltage within one-sixth of the DC-link voltage by construction, a hard bound rather than a statistical tendency. But the constraint exacts a price: it strips away the redundant switching states that a conventional modulator uses to center each leg’s pulse within the switching period, pushing spectral energy from the carrier sidebands down into low-order harmonics and raising the current distortion. The trade-off between common-mode voltage and harmonic distortion is therefore not an implementation artifact but an inherent consequence of which switching combinations the modulator is allowed to use.

The proposed scheme, called a single-carrier hybrid switching mechanism, exploits this insight by switching between two established modulation maps according to the instantaneous polarity of the phase references. When the reference of phase A is positive or the reference of phase C is negative, the controller applies the first map, which preserves the full vector set and delivers clean current waveforms. Over the complementary interval, it applies the second map, which enforces the restricted triplet set and bounds the common-mode voltage. Because the two polarity tests define angular intervals whose union covers exactly two-thirds of the fundamental period, the low-common-mode map is engaged over a fixed, precisely known one-third of each cycle. The mean-square common-mode voltage then combines across these disjoint intervals, yielding a reduction that is partial by design and predictable rather than opportunistic.

Crucially, the changeover between the two maps is seamless in a mathematically precise sense. Each transition instant coincides exactly with the zero-crossing of the very reference whose polarity triggers it, and at such an instant the affected leg rests at the zero level regardless of which map is in force. The modulating function is therefore continuous across the changeover, no step is impressed on the volt-second reference, and no low-order harmonics are injected at the fundamental frequency. The authors also show that the scheme neither improves nor degrades the natural balancing of the neutral point: the redundant small vectors that inject a net DC component into the mid-point occur in pairs with equal and opposite contributions, and the single-carrier construction distributes their dwell times symmetrically, so the average neutral-point current over a fundamental period remains zero under balanced conditions.

The implementation cost is remarkably low. Where level-shifted schemes for a three-level converter typically require two carriers per phase and supporting look-up tables, the new method needs one carrier, two comparisons and one subtraction per leg per sampling instant, plus a single two-term polarity test for the whole modulator. No additional sensors, analog-to-digital channels or memory are required, and the material cost of the converter is unchanged. Because both maps produce exactly one turn-on and one turn-off transition of the active device per leg per carrier period, differing only in where that transition falls within the period, the number of commutations and hence the switching losses are identical across the conventional and hybrid schemes. The common-mode reduction is thus obtained at no switching-loss penalty, a meaningful distinction from more aggressive zero-common-mode schemes that report increased commutation counts as the price of full elimination.

Experimental verification was carried out on a one-kilowatt-rated prototype built around silicon carbide MOSFETs, switching at 20 kilohertz with a 140-volt DC link, a one-millihenry output inductor and a resistive load, controlled by a development board built around a TI TMS320F28379D digital signal processor. Because of hardware limits on load capacity, the comparative tests ran at reduced power. Under full modulation, the conventional third-harmonic injection scheme produced current distortion of about 6.3, 6.1 and 6.3 percent in the three phases but a common-mode voltage of 46.6 volts root-mean-square, while the conventional carrier-based low-common-mode scheme cut that voltage to 23 volts at the cost of distortion rising as high as 11.3 percent. The hybrid mechanism landed in between, at 36.3 volts, a 22 percent reduction, with distortion of 9.3, 6.5 and 6.4 percent, closely tracking the high-quality benchmark rather than the distorted one.

The pattern repeated at half modulation, where the conventional injection scheme yielded 28 volts of common-mode voltage with distortion near 10 percent, the carrier-based scheme dropped to 9 volts but distortion climbed to nearly 20 percent in one phase, and the hybrid scheme settled at 14 volts with distortion between 11.8 and 14.1 percent. Notably, the proportional reduction held at both operating points despite very different absolute voltage levels, which the authors attribute to the fact that the improvement stems from changing the admissible switching set over a defined third of the fundamental period, not from any averaging, filtering or feedback action. The analysis also explains a subtle asymmetry in the data: phase A, whose reference passes through zero within the constrained interval and therefore suffers the narrowest pulses, degrades roughly twice as much as the other two phases in every test, a direct consequence of the geometry rather than an experimental artifact.

A detailed loss study using a manufacturer device model for the silicon carbide switches found the three strategies thermally indistinguishable. Conduction losses dominated, contributing more than 93 percent of the roughly 110-watt total semiconductor dissipation at full modulation, with the outer transistors in each leg absorbing about five times the loss of the inner devices. Total losses across the three schemes spanned only 0.12 percent, and peak junction temperatures differed by just 0.2 kelvin. On the controller, the hybrid scheme’s extra arithmetic amounts to an estimated 0.08 to 0.13 microseconds of incremental execution time, well under one percent of the 50-microsecond control window, because the hardware comparator handles the carrier comparison and the processor merely updates registers and evaluates one sign test. The authors are explicit about the method’s limits: common-mode voltage is reduced, not eliminated, so applications demanding zero common-mode voltage still require more restrictive vector schemes. They point to electric vehicle traction and charging, transformerless grid-tied converters and industrial machine drives as promising application areas, and list extensions to closed-loop drives under dynamic loading, deeper thermal analysis and converters with more than three levels as future work.

Subject of Research: A hybrid switching modulation strategy for reducing common-mode voltage and harmonic distortion in three-phase three-level T-type inverters

Article Title: Single-carrier hybrid switching strategy for common-mode voltage and harmonic mitigation in multilevel T-type inverters

Article References: Mohammed, S. A. Q., Hakami, S. S., Kassas, M., & AlMuhaini, M. (2026). Single-carrier hybrid switching strategy for common-mode voltage and harmonic mitigation in multilevel T-type inverters. Results in Engineering, 32, Article 113577. https://doi.org/10.1016/j.rineng.2026.113577

Image Credits: AI Generated

DOI: 10.1016/j.rineng.2026.113577

Keywords: power electronics, T-type inverter, common-mode voltage, total harmonic distortion, modulation strategy, silicon carbide MOSFET, neutral-point clamped, motor drives, renewable energy, switching losses, DSP control, three-level converter