Compact AES chip designs slash logic use by 94 percent and halve power draw

Engineers have unveiled two ultra-compact hardware designs for the Advanced Encryption Standard that shrink the silicon footprint of AES-128 by as much as 94.2 percent and cut power consumption by roughly half, according to a study published on 4 October 2026 in the journal Discover Electronics. The work, led by M. Mehedi Hasan with Raisa Ahmed, Md. Tawfiq Amin and Md. Mozahidul Islam, targets the growing fleet of Internet of Things devices, embedded systems and hardware security platforms that need strong encryption but cannot afford the logic resources, power budgets and design complexity of conventional AES hardware.

AES is the most widely adopted symmetric encryption standard, standardized by the National Institute of Standards and Technology in 2001 and deployed across wireless communications, secure storage, financial applications and military systems. The algorithm processes 128-bit data blocks with 128-bit keys, combining substitution, permutation, diffusion and key-dependent operations across multiple rounds. Its security credentials are well established, but the hardware cost is not trivial. Conventional implementations often instantiate multiple parallel functional units, dedicated round-processing blocks and extensive key scheduling circuitry to maximize throughput, which translates into substantial logic utilization and power draw. That trade-off makes them a poor fit for battery-powered devices and low-cost security platforms, where area, energy and computational efficiency dominate the design requirements.

The new paper addresses this gap with two progressively optimized architectures: a Round Key-Based AES design and a Serial Key-Based AES design. The Round Key-Based architecture follows the well-established iterative approach to hardware cryptography. Rather than dedicating a separate hardware circuit to each of the encryption rounds, it reuses a single datapath under the supervision of a finite state machine, or FSM. The datapath contains a 128-bit state register and one instance each of the SubBytes, ShiftRows, MixColumns and AddRoundKey transformation units, with a feedback path returning the processed state to the register after every round. A round counter advances from zero to ten while the FSM generates enable signals for each processing stage, coordinating the initial key addition, the nine standard rounds and the final round in which MixColumns is disabled according to the AES standard.

A dedicated key expansion module rounds out the Round Key-Based design. Instead of precomputing and storing all eleven round keys, the architecture generates the required key iteratively during encryption. The 128-bit cipher key is divided into four 32-bit words, and the AES key schedule transforms and XOR-chains these words to produce the 44 words that form the round keys. This iterative generation eliminates the need for large key storage memories while remaining compliant with the AES-128 specification. Both architectures were modeled in VHDL, functionally verified in ModelSim and synthesized with Quartus II, a flow the authors used consistently across verification, timing analysis and resource measurement.

The Serial Key-Based architecture pushes the optimization considerably further. It adopts a fully serial processing methodology in which encryption and decryption operate on a single byte of data at a time through a shared datapath. The FSM maintains three counters, tracking the round from zero to ten, the column from zero to three and the byte index from zero to fifteen, and generates the appropriate enable signals for each transformation block at every step. ShiftRows is implemented through index remapping rather than physical data movement, reducing routing overhead. Perhaps most notably, the design eliminates conventional key expansion hardware altogether, performing direct serial key integration through byte-wise addition in the AddRoundKey module. Because only one byte is processed at a time, no dedicated round-key storage memory is required. A single shared S-Box, the substitution unit that typically consumes a large share of AES hardware resources, serves the entire architecture, and the same hardware structure supports both encryption and decryption through a mode control signal.

The measured results are striking. The standard AES implementation used as the reference required 9,998 logic elements and 524 registers. The Round Key-Based design cut that to 2,372 logic elements, a 76.3 percent reduction, and 274 registers. The Serial Key-Based architecture went further still, requiring only 580 logic elements, a 94.2 percent reduction, and just 139 registers. Lookup table usage followed the same trajectory: reductions of approximately 77.9 percent for the Round Key-Based design and 95.3 percent for the Serial Key-Based design, which needs only 441 lookup tables. The authors attribute these savings to iterative processing, FSM-controlled operation, shared datapath components, the elimination of duplicated round-processing hardware and, in the serial design, the shared S-Box and serial key mechanism.

Performance did not suffer for the area savings. The Round Key-Based architecture achieved a maximum operating frequency of 121.70 megahertz, about 5.2 percent above the standard implementation, while the Serial Key-Based design reached 135.65 megahertz, an improvement of roughly 17.3 percent. Critical path delay fell from 8.64 nanoseconds in the reference design to 8.21 nanoseconds and then 7.37 nanoseconds, the latter a 14.7 percent reduction. The serial architecture also achieved a throughput of 17.36 gigabits per second, the highest among the evaluated designs. The authors attribute the timing gains to the simplified datapath structure, reduced routing congestion, minimized combinational logic depth and the centralized FSM-based control strategy.

Power consumption dropped nearly in parallel. The standard AES design consumed 482.51 milliwatts, while the Round Key-Based and Serial Key-Based architectures consumed 241.86 and 241.18 milliwatts respectively, reductions of approximately 49.9 and 50.0 percent. The authors attribute the power savings primarily to lower logic utilization, reduced switching activity, a smaller routing network and the elimination of redundant processing units, with the serial design benefiting additionally from extensive hardware sharing and byte-at-a-time datapath execution that minimizes dynamic power dissipation. Register-transfer-level analysis after synthesis confirmed that only a single datapath instance is used throughout encryption, with extensive multiplexer networks handling state feedback, round selection and routing of intermediate results, and no redundant datapath resources observed.

Functional correctness was verified in two complementary ways. ModelSim simulations applied a standard 128-bit test vector, encrypting the plaintext 00112233445566778899AABBCCDDEEFF with the key 000102030405060708090A0B0C0D0E0F to produce the expected ciphertext DEE74FBD467D63FD6B6AFBAD08099158, with waveforms confirming correct operation of all four transformation stages and successful decryption. The team also ran image encryption and decryption experiments on multiple color images: after encryption the cipher images appeared noise-like with no recognizable structure, and after decryption the originals were recovered with no observable distortion. The authors position the designs for lightweight cryptography, secure embedded systems, IoT devices, wireless sensor networks and edge computing platforms, and note that the comparison with previously published AES implementations, summarized in their quantitative tables, supports the claimed balance among security, throughput, area efficiency and energy consumption. As with any synthesis-based study, the reported figures reflect the Quartus II toolchain and target devices used, and the throughput figures apply to the specific architecture evaluated rather than serving as a general benchmark for all AES hardware.

Subject of Research: Compact control-optimized AES-128 hardware architectures for resource-constrained devices

Article Title: Control optimized AES-128 cryptographic architectures achieving 94.2% logic reduction and 50% power savings

Article References: Hasan, M. M., Ahmed, R., Amin, M. T., & Islam, M. M. (2026). Control optimized AES-128 cryptographic architectures achieving 94.2% logic reduction and 50% power savings. Discover Electronics, 3(1), Article 140. https://doi.org/10.1007/s44291-026-00295-8

Image Credits: AI Generated

DOI: 10.1007/s44291-026-00295-8

Keywords: AES-128, cryptography, VLSI, FPGA, IoT security, lightweight cryptography, FSM control, hardware optimization, embedded systems, low-power design, VHDL, serial datapath