In the relentless quest to push the boundaries of semiconductor technology, researchers from the National University of Singapore (NUS) in collaboration with Applied Materials have unveiled a groundbreaking advancement that promises to reshape the future of microchip manufacturing. As the global semiconductor market races towards the trillion-dollar mark propelled by demand for faster computing, smarter artificial intelligence, and more compact electronic devices, addressing fundamental physical constraints in chip architecture has become a critical imperative. A newly developed atom-thin coating — a monolayer of crystalline tungsten disulfide (WS₂) — presents a transformative solution, elegantly overcoming a pressing bottleneck in chip miniaturization with profound implications for speed, reliability, and efficiency.
Traditional transistor miniaturization has long driven performance gains in integrated circuits. However, as transistors and their connecting copper wires shrink into the sub-10 nanometer regime, the surrounding protective layers—essential for maintaining electrical integrity—resist further reduction. These layers, typically tantalum-based barrier and liner materials, must maintain a minimum thickness of around four nanometers. In future nanoscale interconnects, these coatings may consume nearly half the cross-sectional area of the copper wiring, severely throttling electrical conductivity and device speed. The NUS and Applied Materials team’s innovation resides in synthesizing an ultrathin WS₂ film, less than a nanometer thick, that simultaneously fulfills the dual role of barrier and liner, drastically slashing thickness without compromising performance.
This pioneering coating, grown on industry-standard 200-millimeter silicon wafers using a low-temperature thermal atomic layer deposition process at 350 degrees Celsius, exemplifies a remarkable confluence of scalability and compatibility. The process avoids plasma, guaranteeing conformal deposition with precise thickness control down to a single atomic layer. Notably, this method achieves uniform coverage in high aspect ratio trenches, exceeding 95% conformity even at depth-to-width ratios of 10:1. Such attributes position this WS₂ monolayer as a viable drop-in replacement within existing semiconductor fabrication lines, bridging the formidable divide between laboratory breakthroughs and industrial applicability.
The WS₂ film’s threshold thickness of approximately 0.7 nanometers contrasts starkly with the conventional six nanometer standard, enabling a future 20-nanometer-wide copper wire to retain over 90% of its conductive cross-section. This relatively unobstructed copper path translates into reduced electrical resistance and elevated current carrying capacity, directly enhancing chip speed and energy efficiency. Extensive electrical testing demonstrated a monumental reduction in resistance—exceeding a factor of one million—compared to uncoated counterparts. The superior adhesion properties offered by the WS₂ liner promote smooth and continuous copper film formation, vital for producing reliable, defect-free interconnects at such ultrathin dimensions.
Beyond adhesion, the WS₂ monolayer serves as a robust diffusion barrier that impedes copper migration into silicon and dielectric materials under thermal and electrical stress. In accelerated aging tests, conventional barrier-free copper rapidly reacted with underlying silicon, forming deleterious intermetallic compounds and defect clusters. In stark contrast, WS₂-coated samples exhibited no such degradation, maintaining pristine interfaces even after prolonged exposure. Remarkably, devices using the atomically thin barrier exhibited projected lifetimes surpassing unprotected designs by an order of magnitude, signaling a dramatic leap in device durability.
Central to the WS₂ film’s efficacy is its polycrystalline structure composed of myriad tiny grains and grain boundaries arranged in random orientations. Unlike continuous single crystals, where aligned grain boundaries can form direct diffusion channels, the staggered grain orientation in multilayer WS₂ films creates a complex labyrinth that frustrates copper atom penetration akin to the staggered offsets in a well-built brick wall. This insight, derived from computational modeling by NUS chemists, identifies nanoscale grain architecture as a key parameter in optimizing barrier functionality, challenging the entrenched paradigm that perfect crystallinity is always advantageous.
The discovery that a single atomic layer can supplant the combined barrier and liner stack confronts long-held assumptions in semiconductor interconnect design. Prior industry standards dictated separate layers with cumulative thicknesses of several nanometers to provide necessary protection and adhesion. By collapsing these essential roles into an atomically thin WS₂ sheet, researchers open new vistas for continuing Moore’s Law scaling into unprecedented regimes. Professor Silvija Gradečak, co-director of the NUS-Applied Materials Corporate Lab, emphasizes that this fundamental shift in approach heralds a new class of interconnect architectures tailored to atomically precise materials engineering.
The process’s compatibility with low thermal budgets—vital for avoiding damage to complex multilayer device stacks—and its wafer-scale uniformity underscore its readiness for integration into contemporary manufacturing ecosystems. These breakthrough properties allow semiconductor producers to adopt WS₂-based coatings without extensive equipment overhauls or processing disruptions, facilitating rapid technology transfer. Dr. Hippolyte Astier highlights that such advancements transcend the immediate generation of chips, positioning the industry to harness this technology across multiple forthcoming innovations extending out to 2037 and beyond.
Applied Materials’ Director of Engineering, Dr. John Sudijono, notes the criticality of merging academic ingenuity with industrial constraints through the Corporate Lab framework. The collaborative environment enabled iterative validation of WS₂ films under realistic fabrication conditions, ensuring the material meets demanding reliability, scalability, and process compatibility benchmarks. This convergence of theory, experimentation, and commercialization is essential to bridging the notorious gulf between laboratory demonstrations and full-scale production deployments in semiconductor manufacturing.
Looking forward, the team is exploring refined control over WS₂ grain orientation and microscopic interface phenomena to fine-tune long-term stability and electrical behavior. Further studies aim to exploit the low-temperature vapor-phase growth technique to deposit other two-dimensional materials within diverse chip components, expanding the scope of atomic-scale coatings in integrated circuit design. This foundational research not only sets a new standard for interconnect barriers and liners but also signals the inception of a broader materials revolution in microelectronics.
The ultrathin WS₂ monolayer innovation thus represents a monumental stride towards sustaining the pace of semiconductor evolution. By ingeniously combining barrier and liner functionality into a single atomic layer with industrially scalable fabrication, this discovery resolves a pressing miniaturization bottleneck, empowering the continuation of chip performance scaling in an era where every nanoscale dimension counts. As the semiconductor industry confronts the ultimate physical limits of transistor and interconnect shrinking, atomically precise materials like WS₂ will be vital enablers of future computational breakthroughs, underpinning the technology transformations of tomorrow.
Subject of Research: Not applicable
Article Title: Low-temperature wafer-scale growth of ultrathin tungsten disulfide for bifunctional interconnect barriers and liners
News Publication Date: 31-Mar-2026
Web References: https://doi.org/10.1038/s41928-026-01592-6
Image Credits: College of Design and Engineering, NUS
Keywords
Semiconductors, Microelectronics, Materials engineering, Materials science
Tags: advanced semiconductor materialsatom-thin tungsten disulfide coatingchip miniaturization technologycopper wiring barrier layersintegrated circuit performance enhancementnanoscale interconnect materialsnext-generation chip architecturereliability in nanoscale electronicssemiconductor manufacturing innovationsemiconductor transistor scalingsub-10 nanometer transistor developmenttungsten disulfide in microchips
