Smart Power-Gate Placement Slashes Energy Use in Multiplexer and Demultiplexer Circuits

Engineers designing the data-routing circuits that shuttle information inside memory chips, processors and communication interfaces now have a new lever to pull: where, not just how, to place the transistors that switch off idle logic. A study published in Discover Electronics on 22 October 2026 reports that simply relocating a high-threshold-voltage power-gating transistor to a topology-dependent stage of cascaded transmission-gate multiplexer and demultiplexer circuits can cut power consumption by up to 40 percent while, in one case, actually speeding the circuit up rather than slowing it down.

The work, carried out by Mahfuzur Rahman Kabbo and Md. Tawfiq Amin, targets a long-standing tension in low-power chip design. As CMOS technology has scaled into the nanometer regime, leakage current has become an increasingly important share of total power dissipation, driven by lower threshold voltages, thinner gate dielectrics and higher transistor density. Multi-threshold CMOS, or MTCMOS, addresses this by placing high-threshold-voltage sleep transistors between the power rails and the logic block, choking off the subthreshold leakage path when the circuit is idle. But conventional power gating carries a price: the added series resistance of the sleep transistor increases propagation delay, and dedicated sleep-control networks add area, voltage drop and wake-up latency.

The central hypothesis of the new work is that the performance of power gating in a transmission-gate circuit depends not only on the properties of the high-threshold device itself but also on its topological location within the circuit. Each stage of a cascaded transmission-gate system contributes differently to power consumption, signal propagation and capacitive loading, so the position of the gated stage can shape both leakage characteristics and timing behavior. The authors argue that exploiting this topology-dependent behavior can yield a more efficient gating scheme than past approaches based solely on leakage minimization.

Transmission-gate logic is widely used for multiplexing and demultiplexing because it provides full-swing signal transmission, low static power dissipation and improved signal integrity compared with pass-transistor alternatives. A transmission-gate 4:1 multiplexer can be built as a cascaded tree of three 2:1 cells, and a 1:4 demultiplexer as three cascaded 1:2 cells. The researchers simulated their designs in Cadence Virtuoso using the GPDK 090 90-nanometer CMOS process at a supply voltage of 1.2 volts, first characterizing standard-threshold and high-threshold PMOS device variants through DC simulation to extract threshold voltage, on-resistance and leakage current.

The proposed architecture adds only two transistors to each circuit and requires no dedicated sleep network. A select-controlled high-threshold PMOS header is inserted at a topology-dependent transmission-gate stage, and a second block-level header is applied at the testbench supply port. In the 4:1 multiplexer, the header is placed in the output-stage cell, the one that drives the external output node directly, because that cell’s PMOS leakage dominates in the converging tree while the first-stage cells are kept at standard threshold to preserve fast input transitions. In the 1:4 demultiplexer, the gating is applied to the first-stage cell, whose virtual supply then extends leakage suppression across all four output paths through a single header device.

The measured results diverge sharply between the two topologies. The power-gated multiplexer reduced average power from 177.500 nanowatts to 106.500 nanowatts, a 40.0 percent reduction, but paid a 16.0 percent delay penalty, with propagation delay rising from 38.910 picoseconds to 45.150 picoseconds. Even so, the power-delay product improved 30.4 percent, from 6.907 attojoules to 4.808 attojoules, and the energy-delay product fell 19.2 percent. The demultiplexer fared better on every metric: power dropped 28.6 percent, from 224.097 nanowatts to 159.972 nanowatts, and delay simultaneously fell 57.2 percent, from 63.527 picoseconds to 27.188 picoseconds, yielding a 69.4 percent lower power-delay product and an 86.9 percent lower energy-delay product.

Analytical RC-delay models explain why the two circuits behave so differently. In the converging multiplexer tree, the header resistance sits in series with the output discharge path, increasing the RC time constant and directly predicting the observed delay increase; the authors note that although a first-order Elmore model overestimates absolute delays in deep-submicron CMOS, the predicted delay ratio captures the physical trend. In the diverging demultiplexer tree, the first-stage header lowers the internal virtual supply, which reduces charge accumulation in the unselected branches and mitigates capacitive coupling and charge-redistribution contention during select transitions, allowing internal nodes to settle faster. The authors caution that this behavior is highly topology- and transition-dependent and should not be read as a universal consequence of reduced voltage swing, since a lower internal swing also compresses the dynamic output-high level and demands careful trade-offs with noise margins.

Robustness was verified through several layers of simulation. Static DC sweeps confirmed that the transmission-gate circuits, which act as passive switching networks with a linear pass-through voltage transfer characteristic rather than an inverter-like switching threshold, preserve adequate high-level noise margins, with any attenuation introduced by the headers remaining minimal and bounded. Process-voltage-temperature analysis across five process corners, temperatures from 0 to 85 degrees Celsius and supply voltages of 1.08, 1.2 and 1.32 volts showed that the relative improvement of the hybrid design over the conventional baseline is preserved across corners, with the slow-slow corner producing worst-case delay and the fast-fast corner worst-case power. Voltage scaling from 0.8 to 1.5 volts showed reliable operation within 0.8 to 1.3 volts, above which virtual-supply regulation breaks down and power, delay and power-delay product rise abruptly.

Statistical validation came from 1000-run Monte Carlo simulations at the typical-typical corner. The hybrid multiplexer showed a mean delay of 44.44 picoseconds with a standard deviation of 2.03 picoseconds, a coefficient of variation of 4.57 percent, while the demultiplexer yielded a mean of 25.36 picoseconds with a standard deviation of 2.83 picoseconds and a coefficient of variation of 11.16 percent, corresponding to a three-sigma range of 16.87 to 33.85 picoseconds. The authors attribute the demultiplexer’s higher spread to the topological location of the header, whose mismatch is distributed through the diverging tree rather than absorbed locally, but both circuits remained within the 10 to 20 percent coefficient-of-variation range typical of sub-100-nanometer CMOS variability. A load-capacitance sweep from 0 to 50 femtofarads showed monotonically increasing delay for both circuits, with the multiplexer remaining very stable and the demultiplexer more sensitive at higher loads.

The hardware cost of the scheme is modest: the conventional baselines use 12 transistors across three transmission-gate cells, and the hybrid designs add exactly two high-threshold PMOS transistors, a 16.7 percent increase in transistor count excluding inverters. Leakage suppression reached approximately 60 percent in the multiplexer and 31.2 percent in the demultiplexer. The authors generalize their finding into a stage-selection principle: first-stage power gating adds output-path series resistance in converging structures, causing a predictable delay penalty, while in diverging structures it reduces charge redistribution across downstream branches and can improve energy and delay simultaneously under the conditions characterized. They note the principle is conceptually extensible to larger trees such as 8:1 multiplexers and 1:8 demultiplexers, and to time-division multiple access architectures where an N:1 multiplexer interleaves channels onto a shared serial line, but quantitative characterization of such higher-order designs would require additional transistor-level simulation and is left for future work.

Subject of Research: Topology-aware high-threshold-voltage MTCMOS power gating of cascaded transmission-gate multiplexer and demultiplexer circuits in 90 nm CMOS

Article Title: Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX

Article References: Kabbo, M. R., & Amin, M. T. (2026). Topology-aware HVT MTCMOS power gating for power–delay optimization of cascaded transmission-gate MUX and DEMUX. Discover Electronics, 3(1), Article 151. https://doi.org/10.1007/s44291-026-00304-w

Image Credits: AI Generated

DOI: 10.1007/s44291-026-00304-w

Keywords: power gating, MTCMOS, multiplexer, demultiplexer, transmission gate, leakage power, 90 nm CMOS, power-delay product, energy-delay product, PVT analysis, Monte Carlo simulation, low-power VLSI