Liquid Cooling Keeps 51.2 Tbit/s Co-Packaged Optics Within Safe Temperatures

As data centers strain under the demands of artificial intelligence workloads, the optical interconnects that move data between chips are being squeezed closer and closer to the electronics that generate enormous amounts of heat. A new study published in Frontiers of Optoelectronics reports a liquid-cooling thermal management design that, in both simulation and bench-top experiment, keeps a 51.2 Tbit/s co-packaged optics (CPO) system within its temperature limits: the 750 W switch chip peaks at 97.3 °C in simulation and 98.3 °C in testing, while the surrounding optical modules stay far cooler and nearly uniform in temperature.

Co-packaged optics is an answer to a problem that has been building for years. In conventional data center architectures, optical modules sit on the board some distance from the switch chip, connected by long electrical traces. As bandwidth climbs, those long interconnects degrade signal quality and drive up power consumption. According to Cisco statistics cited in the study, switch chip power consumption grew roughly eightfold between 2010 and 2022, and in a 51.2 Tbit/s switch system the optical modules alone can account for more than half of total system power. CPO tackles this by integrating the optical engines and the switch chip on the same substrate, dramatically shortening the electrical interconnection distance.

That integration, however, creates a thermal dilemma. The switch chip in a 51.2 Tbit/s CPO system can dissipate 750 W, corresponding to a heat flux of about 1.79 W/mm², while each of the eight optical modules in the modeled system dissipates 64 W at roughly 0.2 W/mm². The optical devices sitting millimeters away from this furnace are exquisitely temperature-sensitive, particularly micro-ring modulators, whose operating wavelength shifts by approximately 0.1 nm for every 1 °C of temperature change. In dense wavelength division multiplexing systems, where channel spacing is typically 0.4 to 0.8 nm, that sensitivity means excessive temperature differences between modules increase insertion loss and can cause crosstalk between channels. The study therefore set a strict uniformity target: no more than 4 °C difference among the optical modules.

Industry temperature targets, referencing limits established by Intel, require the switch chip junction temperature to stay below 105 °C and the optical module junction temperature below 100 °C. The research team, led by Senhan Wu and colleagues, designed two independent heat sinks to meet these needs. For the high-flux switch chip, they chose a manifold microchannel heat sink attached through a TIM1.5 package, in which the chip and heat sink are bonded directly with thermal interface material rather than reflowed solder. Manifolds split and distribute the coolant across the microchannels, cutting the pressure drop that plain microchannel cold plates would otherwise impose and reducing pump power. For the lower-power optical modules, where uniformity matters more than raw cooling capacity, they used a parallel microchannel arrangement that delivers coolant at the same inlet temperature to every module’s cold plate.

The design was optimized computationally using the incompressible, steady-state Navier–Stokes equations, assuming laminar flow with constant fluid properties, solved in 6 sigmaET software. Reynolds number calculations showed the flow remains laminar below 6 L/min inlet flow rate. The team first examined junction temperature and pressure drop versus flow rate in a 25.6 Tbit/s configuration and found that chip temperature gains flatten as flow rate rises while pressure drop grows exponentially, leading them to select 4 L/min as the optimal operating point. Structural parameters were then tuned: microchannel width of 200 µm for the switch chip heat sink, careful selection of channel depth, deeper manifold channels to reduce pressure drop, and a 1-in-2-out manifold layout that balanced cooling efficiency against pumping cost.

One of the more inventive elements is a locally wavy microchannel. Wavy channels disturb the boundary layer at the channel bottom and enhance heat transfer, and a fully wavy design performed best in simulation—but doubled the pressure drop at 4 L/min. The researchers instead applied the wavy geometry only over the hotspot at the center of the switch chip, leaving straight channels elsewhere. This preserved most of the thermal benefit while keeping the pressure penalty within an acceptable range, and the wavy section length can be adjusted to trade cooling capacity against pressure drop as needed.

With the optimized design, simulation of the full 51.2 Tbit/s system, using deionized water coolant at a 20 °C inlet temperature, copper heat sinks, and thermal grease with roughly 120 µm bond line thickness, yielded a switch chip junction temperature of 97.3 °C, a maximum optical module junction temperature of 31.3 °C, and a temperature difference among the optical modules reduced from 2.4 °C before optimization to 1.2 °C after—well inside the 4 °C uniformity requirement and with pressure drop essentially unchanged.

To validate the model, the team built a thermal test platform in which thermal test chips were flip-bonded to a test board to imitate the CPO, and heat sinks fabricated by direct metal laser sintering formed integrated, sealed structures that avoid leakage. Thermocouple probes inserted at the bottom center of each chip monitored junction temperatures, with additional sensors at the coolant inlet and outlet, a differential pressure gauge across the ports, and a flow meter on the inlet hose. Across the tested flow rates, the maximum deviation between simulated and measured switch chip temperature was 2.3 °C at 1 L/min, a difference within 4%, and the measured pressure drop, while slightly lower than simulated, followed the same exponential trend with flow rate. Optical module temperatures matched simulation within 1.5 °C, and even at the lowest flow rate the measured temperature difference among modules never exceeded 1.7 °C.

Taken together, the simulation and measurement results support the conclusion that the designed heat sink satisfies the heat dissipation demands of a 51.2 Tbit/s bandwidth CPO system.

The study’s scope is a specific modeled and tested configuration rather than a commercial product, and the chip power parameters were adjusted from a 2022 Optical Internetworking Forum forecast to reflect real market power consumption, with the authors noting that actual switch chips already exceed that prediction. Still, the work demonstrates a concrete path for liquid cooling in co-packaged optics at a bandwidth where the authors argue traditional air cooling may no longer suffice, and it offers a design basis for future optoelectronic integration in wavelength division multiplexing and micro-ring device applications. The authors suggest liquid-cooled heat dissipation could become a key thermal management technology for server clusters in future data centers.

Subject of Research: Liquid-cooling thermal management for high-bandwidth co-packaged optics systems

Article Title: Simulation and experimental investigation of liquid-cooling thermal management for high-bandwidth co-packaged optics

Article References: Wu, S., Wen, S., He, H., Feng, J., Chen, C., & Xue, H. (2025). Simulation and experimental investigation of liquid-cooling thermal management for high-bandwidth co-packaged optics. Frontiers of Optoelectronics, 18(1), Article 11. https://doi.org/10.1007/s12200-025-00156-4

Image Credits: AI Generated

DOI: 10.1007/s12200-025-00156-4

Keywords: co-packaged optics, liquid cooling, microchannel heat sink, thermal management, data centers, switch chips, optical modules, thermal crosstalk, Navier-Stokes simulation, manifold cold plate, temperature uniformity, 51.2 Tbit/s