In the relentless pursuit of smaller, faster, and more efficient semiconductor devices, two-dimensional (2D) materials have emerged as transformative candidates poised to revolutionize transistor technology. Among these materials, monolayer tungsten diselenide (WSe₂) has garnered intense interest due to its promising electronic properties and atomically thin structure. Recent advancements have now demonstrated a significant leap in the performance of p-type WSe₂ transistors, overcoming long-standing hurdles that have hindered their practical application and bringing them closer to integration into next-generation complementary metal-oxide-semiconductor (CMOS) technologies.
Historically, the semiconductor industry has struggled to replicate the high performance of n-type devices when developing their p-type counterparts using 2D materials. This discrepancy has largely stemmed from challenges inherent to p-type transistor fabrication, including lower carrier mobility and difficulties in achieving low-resistance electrical contacts. The new study by Sun, Gao, Li, and colleagues addresses these critical limitations head-on, showcasing p-type monolayer WSe₂ transistors with unprecedented hole mobility and minimized contact resistance values, all realized at room temperature.
One of the fundamental hurdles in p-type 2D semiconductors has been the prevalence of defect states, such as vacancies or impurities, that act as charge traps and scattering centers, severely degrading electrical performance. The novel approach reported in this work introduces a precisely controlled, industry-compatible oxygen-incorporated process that effectively heals these defect states within the monolayer WSe₂. By oxygen-tuning, the researchers have managed to passivate detrimental defects, thereby restoring and enhancing the intrinsic electronic properties of the material without compromising its structural integrity.
This oxygen-assisted healing method significantly improves hole mobility, achieving a record value of 137 cm²/V·s—a considerable advancement over previously reported figures in similar materials and device configurations. Additionally, contact resistance, a critical parameter influencing the overall transistor speed and power consumption, was remarkably reduced to approximately 560 Ω·µm. This reduction signifies enhanced charge injection efficiency from metal electrodes into the semiconductor, a notoriously difficult issue in p-type 2D devices.
The study further validates the practical viability of these high-performance p-type WSe₂ transistors by scaling the channel length down to an astonishing 45 nanometers, a benchmark aligning with the stringent dimensions required for future-generation logic devices. At this scale, the transistor exhibits an on-state current density of 1,245 µA/µm, a value that rivals or surpasses many state-of-the-art n-type analogues. Equally critical, the device maintains an exceptionally high on/off current ratio of approximately 10⁹, indicating excellent switching behavior and minimal leakage currents—essential attributes for energy-efficient digital circuits.
Delving into the transistor’s architecture, the use of monolayer WSe₂ as the channel material harnesses its direct bandgap and strong spin-orbit coupling, features that inherently favor high mobility and reduced short-channel effects. The atomic-scale thinness of the monolayer also ensures superior electrostatic control by the gate electrode, allowing aggressive device scaling without sacrificing performance or increasing power dissipation.
Moreover, the oxygen-incorporated passivation strategy introduced is highly adaptable and compatible with existing semiconductor manufacturing processes, paving the way for scalable production of these advanced 2D materials-based devices. This compatibility is crucial for industry adoption, addressing a frequent bottleneck wherein innovative lab-scale techniques fail to translate to mass production environments due to complexity or incompatibility with standard fabrication workflows.
The reduction in contact resistance achieved is primarily attributed to the elimination of mid-gap states and defect-induced band bending at the metal-semiconductor interface, facilitating more efficient hole injection. This insight underscores the importance of interface engineering in 2D transistor design and highlights the nuanced interplay between material quality, surface chemistry, and contact architecture.
Importantly, the findings also shed light on the inherent advantages of p-type WSe₂ in complementing n-type transition metal dichalcogenides (TMDs) such as MoS₂, which have previously dominated the landscape. By elevating p-type performance, the study effectively circumvents one of the most significant obstacles preventing balanced, high-performance complementary logic circuits based entirely on 2D semiconductors—a prerequisite for truly revolutionary ultrathin, flexible, and wearable electronics.
From an application perspective, these high-mobility p-type WSe₂ transistors enable the design of complementary transistor pairs that operate with improved energy efficiency, higher speeds, and reduced heat generation. Such characteristics are invaluable for powering emerging technologies ranging from advanced processors and memory devices to novel optoelectronic systems and sensor arrays.
The researchers’ work also opens intriguing avenues for exploiting oxygen chemistry within other 2D materials systems, potentially generalizing this defect-healing paradigm to a broader range of semiconducting monolayers that suffer from similar performance bottlenecks. It invites a paradigm shift in how defects, often viewed as detrimental by default, can be strategically managed and harnessed to enhance device functionality.
In summary, this breakthrough exemplifies a critical step forward in bridging the performance gap for p-type 2D semiconductor devices, aligning their capabilities with or beyond those of their n-type counterparts. The marriage of tunable oxygen passivation with precise monolayer WSe₂ transistor engineering marks a milestone in the ongoing quest for ultrathin, scalable, and high-performance electronics.
As the semiconductor industry pushes toward the physical and economic limits of silicon-based scaling, innovations like these underpin the transition to more versatile, energy-efficient technologies. Importantly, the demonstrated control over defect states in monolayer WSe₂ using an industry-compatible process ensures that these advances are not confined to the research lab but are positioned for real-world implementation on a commercial scale.
The research further highlights monolayer tungsten diselenide’s promise not only as a channel material with superior intrinsic properties but also as a platform for innovative surface and interface engineering strategies. This dual advantage positions WSe₂-based transistors as front-runners among emerging materials for future complementary transistor technologies.
Looking ahead, the integration of these high-performance p-type devices into complex circuits and systems remains a crucial next step. Efforts focused on large-area synthesis, uniform doping control, and integration with diverse substrate types will be pivotal in fully realizing the commercial potential of monolayer WSe₂ technologies.
In conclusion, the landmark demonstration of high-performance p-type monolayer WSe₂ transistors heralds a new era in 2D semiconductor research and applications. Through meticulous defect passivation and ultrashort channel design, this study offers a powerful blueprint for delivering balanced, scalable, and efficient electronics crucial to the future of computing, communication, and sensory technologies.
Subject of Research: High-performance p-type monolayer tungsten diselenide (WSe₂) transistors.
Article Title: High-performance p-type monolayer tungsten diselenide transistors.
Article References:
Sun, L., Gao, T., Li, X. et al. High-performance p-type monolayer tungsten diselenide transistors. Nat Electron (2026). https://doi.org/10.1038/s41928-026-01637-w
Image Credits: AI Generated
DOI: https://doi.org/10.1038/s41928-026-01637-w
Tags: 2D WSe2 transistor technologycharge trap reduction in tungsten diselenidedefect state mitigation in 2D semiconductorshigh hole mobility in WSe2high-performance p-type monolayer tungsten diselenide transistorslow-resistance electrical contacts in 2D materialsnext-generation CMOS integration with 2D materialsovercoming p-type transistor fabrication challengesroom temperature p-type WSe2 transistorsscalable fabrication of p-type Wtwo-dimensional semiconductor devices
