Graph Neural Networks Learn the Noise of Real Quantum Chips to Rescue Failing Computations

Quantum computers promise calculations that would leave even the largest classical supercomputers stranded, but the machines being built today are noisy, fragile, and error-prone. Every qubit on a superconducting processor leaks energy, loses phase coherence, and misfires during gates, so the raw output of a quantum circuit often bears little resemblance to the answer it was supposed to encode. A research team led by Huaxin Wang and Qiang Chen at the National Supercomputing Center in Zhengzhou and Zhengzhou University, working with colleagues at Nanjing Institute of Technology, has now unveiled a machine learning framework that confronts this problem head-on. Their approach, called graph-enhanced mitigation, or GEM, teaches a neural network to read the physical fingerprint of a quantum chip and use that knowledge to correct the distorted results of quantum computations. The work, published in Quantum Machine Intelligence, was demonstrated on real superconducting hardware, including the 176-qubit Tianyan processor provided by China Telecom, with preliminary workflow testing on Origin Quantum’s Wukong-180 device.

The technique the researchers are targeting is known as quantum error mitigation, a family of methods that differ fundamentally from quantum error correction. Error correction encodes information redundantly across many physical qubits so that mistakes can be detected and reversed during the computation itself, an approach that demands enormous hardware overhead. Error mitigation, by contrast, accepts the noisy output as it arrives and applies classical post-processing to estimate what the ideal, noiseless result would have been. It is the pragmatic choice for the current era of noisy intermediate-scale quantum devices, the NISQ regime famously described by John Preskill, where processors carry tens to a few hundred qubits but no capacity for full fault tolerance. The catch is that mitigation techniques come with their own costs, and those costs tend to balloon as circuits grow.

Two of the most widely used mitigation strategies illustrate the problem. Zero-noise extrapolation runs the same circuit at several artificially amplified noise levels and then extrapolates back to the zero-noise limit, a procedure that multiplies the number of circuit executions and rests on assumptions about how noise scales. Clifford data regression takes a different route: it executes classically simulable Clifford circuits that mimic the structure of the target circuit, learns how noise maps their ideal outputs to noisy ones, and applies that learned correction to the real data. Both approaches, however, are tied to specific circuits or specific noise-scaling assumptions, and their overheads grow uncomfortably with circuit size and complexity. Theoretical work in recent years has also established fundamental sampling lower bounds showing that no mitigation scheme can be universally cheap, which makes it all the more important to squeeze maximum value from every measured sample.

The insight behind GEM is that a quantum processor is not a featureless black box but a physical object whose imperfections are measured, cataloged, and largely stable over time. Calibration routines already track the energy relaxation time T1 and dephasing time T2 of every qubit, the readout error of every measurement, and the error rates of every two-qubit gate on every coupler. Conventional mitigation treats these numbers, at best, as inputs to coarse noise models. The Zhengzhou team instead encodes them directly into the architecture of a graph neural network. Each qubit becomes a node in a graph, and each physical coupling between qubits becomes an edge. The node features carry the local calibration parameters such as T1, T2, and readout errors, while the edge features carry coupling-related quantities like two-qubit gate errors. In this way, the network’s very structure mirrors the wiring diagram of the chip it is trying to understand.

On top of this physically informed representation, the researchers layered two architectural innovations. The first is topology-constrained graph message passing, which means information flows between nodes only along the actual physical couplings of the hardware. Errors on a superconducting chip do not spread uniformly; they propagate through the couplers that connect neighboring qubits, so a network that exchanges information along those same pathways can capture hardware-dependent interactions that a generic neural network would have to rediscover from scratch. The second innovation is a gated local-global residual correction that fuses two views of the problem: qubit-specific features describing what is happening to individual qubits, and circuit-level context describing the state of the computation as a whole. A gating mechanism learns how to weigh these two scales when producing the final correction.

Perhaps the most consequential design choice is parameter sharing. Because the model operates on local nodes and edges rather than on a fixed-size global representation, the same trained network can be applied to circuits of different sizes on the same processor. This is what enables the framework’s headline capability: zero-shot transfer. In the team’s experiments, a model trained on data from 10-qubit random circuits executed on the Tianyan-176 processor was applied, without any retraining, to 16-qubit circuits on the same device. The transferred model achieved a lower mean absolute error than Clifford data regression at the larger size, suggesting that the network had genuinely learned how noise behaves on the chip rather than memorizing quirks of a particular circuit width. At 22 qubits, GEM remained comparable with CDR, and at 10 qubits the two methods were competitive.

The experimental campaign was designed to probe robustness as well as raw accuracy. The researchers evaluated GEM across independent hardware runs, testing whether the learned corrections survive the day-to-day drift that plagues superconducting devices, where T1 times and gate fidelities can fluctuate measurably between calibration cycles. They also examined whether the framework supports reusable mitigation, meaning a single trained model that can serve many different circuits and system sizes through a shared representation of local hardware structure, coupler-level information, and circuit context. Reusability matters enormously in practice: if every new circuit or every new qubit count required a fresh training campaign with fresh quantum measurements, the overhead of learning-based mitigation would quickly erase its benefits. Ablation studies, in which components of the model are systematically removed, confirmed that the informative edge attributes and the graph message passing itself contribute directly to mitigation performance, ruling out the possibility that the gains come from the network’s capacity alone.

The study sits within a rapidly growing body of work applying machine learning to quantum error mitigation. Earlier efforts include neural error mitigation of near-term quantum simulations, learning-based mitigation schemes that train on Clifford circuit data, probabilistic machine learning tailored to variational quantum eigensolvers, and practical machine learning pipelines demonstrated on commercial hardware. What distinguishes GEM is the explicit injection of hardware physics into the learning architecture. Graph neural networks have proven their worth in domains from molecular chemistry to social network analysis, and the team draws on established strategies for pre-training and designing expressive graph networks. By making the coupling graph of the processor the backbone of the model, they ensure that the inductive bias of the network matches the causal structure of the noise, which is precisely what allows a small model trained at one scale to generalize to a larger one.

The implications reach beyond the immediate benchmark results. As quantum processors scale toward hundreds and eventually thousands of qubits, the gap between full error correction and the algorithms users want to run will be bridged, for years to come, by mitigation. Methods that scale gracefully, transfer across circuit sizes, and exploit the wealth of calibration data that hardware operators already collect could substantially extend the computational reach of near-term devices, sharpening everything from variational quantum chemistry to quantum optimization. The authors acknowledge the standard caveats of learning-based approaches, including the need for representative training data and the theoretical sampling costs that no mitigation scheme can escape. Still, the demonstration that a physically informed graph network can match established methods at small scale and outperform them under zero-shot transfer to larger circuits marks a meaningful step. The work was supported by China’s National Key Research and Development Program, and the datasets are available from the corresponding author on reasonable request, offering the community a concrete foundation for building mitigation tools that understand the machines they serve.

Subject of Research: Scalable quantum error mitigation on superconducting quantum processors using physically informed graph neural networks

Article Title: Scalable quantum error mitigation with physically informed graph neural networks

Article References: Scalable quantum error mitigation with physically informed graph neural networks. (n.d.). https://doi.org/10.1007/s42484-026-00462-w

Image Credits: AI Generated

DOI: 10.1007/s42484-026-00462-w

Keywords: quantum error mitigation, graph neural networks, NISQ devices, superconducting qubits, zero-shot transfer, Tianyan-176 processor, zero-noise extrapolation, Clifford data regression, physics-informed machine learning, quantum computing, noise calibration, machine learning