AI surrogate with built-in physics speeds up low-power amplifier design

Designing the amplifiers that sit at the front end of wearable health monitors has always been a balancing act. These circuits must squeeze microvolt-level biosignals such as ECG, EMG and EEG out of noise, interference and manufacturing variability, all while burning as little power as possible. A new study published in Discover Electronics on 7 October 2026 reports a way to automate that balancing act: a deep learning surrogate model, constrained by transistor physics and aware of its own uncertainty, that can replace most of the slow circuit simulations traditionally needed to optimize an ultra-low-power operational transconductance amplifier, or OTA.

The work, carried out by Ashagrie Mekuriaw Kemie and Roy P. Paily, targets a specific amplifier architecture known as the cross-coupled feed-forward (CCFF) OTA, which uses cross-coupling and feed-forward paths to boost gain and bandwidth at low supply voltages. In this topology, the bulk terminals of two transistors are deliberately tied to their own drains, exploiting body-biasing to modulate threshold voltages and improve transconductance efficiency, while bias choices keep the body-to-drain junctions free from significant forward biasing to avoid substrate leakage. The trade-offs involved among gain, bandwidth, noise and power are inherently conflicting, which is precisely why the authors turned to machine learning to explore the design space systematically.

At the heart of the framework is a joint surrogate model built in PyTorch as a fully connected feed-forward neural network. It takes 18 independent design variables as input: 15 transistor sizing parameters, covering channel lengths, widths and numbers of fingers for five transistor groups (active load, bias, input differential pair, current mirror and output), plus three bias voltages covering supply, common-mode input and bias voltage. The network uses four hidden layers with 256, 256, 128 and 64 neurons, SiLU activation functions, and layer normalization after the first hidden layer. Its output layer predicts four quantities at once: DC gain, bandwidth, input-referred noise (IRN) and power consumption, exploiting the correlations among these metrics rather than modeling each in isolation.

What distinguishes this surrogate from a generic black-box predictor is the physics baked into both the training data and the search space. The design space is constructed with the graphical gm/ID methodology, restricting input, output and active-load devices to a gm/ID of roughly 10 to 15 for a balance of gain and noise, while bias and current-mirror devices operate at higher efficiency around 20 to 25. Constraints on intrinsic gain (gm/gds of approximately 150) and saturation margins of about 0.18 to 0.19 act, in the authors’ words, as a physics filter, keeping the optimizer away from non-physical or non-manufacturable solutions. Circuit-level stability is enforced through a phase margin requirement of at least 60 degrees.

The accuracy figures reported are striking. On an independent test set, the model achieved coefficients of determination (R²) of 0.9770 for gain, 0.9321 for bandwidth, 0.9976 for input-referred noise and 0.9771 for power, with low root-mean-square errors across the board. Error distributions were centered around zero with minimal skewness, indicating unbiased predictions, although bandwidth showed a wider error spread, attributed to its higher sensitivity to device parasitics and biasing conditions. Before final training, five-fold cross-validation was used to validate the architecture and training configuration.

Equally important is the framework’s honesty about its own limits. Instead of a single network, the team trained a deep ensemble of 12 independently initialized networks, each trained for 300 epochs on bootstrap-resampled versions of the dataset. The spread among ensemble members serves as an estimate of epistemic uncertainty, flagging poorly explored or highly nonlinear regions of the design space. The calibration checks were convincing: the correlation between predictive uncertainty and absolute prediction error reached 0.9476 for gain, 0.9849 for bandwidth, 0.9269 for IRN and 0.6034 for power, and roughly 99 percent of samples fell within the plus-or-minus two-sigma confidence bounds.

With a trustworthy surrogate in hand, the researchers ran multi-objective optimization using NSGA-II, a genetic algorithm that evolves a population of candidate designs toward a Pareto front of non-dominated trade-offs. Candidates carrying high predictive uncertainty were implicitly penalized, steering the search toward regions that are both high-performing and well-modeled. The resulting Pareto front was smooth and well distributed, with a normalized hypervolume of 0.8468. Across the Pareto-optimal solutions, gain reached up to 79 dB, bandwidth up to 11 kHz, input-referred noise as low as 2.02 microvolts rms, and power consumption down to 5.6 microwatts. Gain improved by roughly 17 dB across the front while bandwidth varied by nearly a factor of four, yet IRN stayed tightly constrained, indicating consistent noise performance throughout.

Six representative operating points emerged from the optimization, including a knee point, a best-practical design, and extremes of gain, bandwidth, noise and power. The knee-point solution, offering the most balanced trade-off, was selected for detailed validation. Across all Pareto-optimal designs, the device-level physics held up: bias and current-mirror transistors operated at gm/ID near 24, input, output and active-load devices stayed within 10 to 15, intrinsic gain remained at approximately 157 to 159, and saturation margins held at about 0.185 to 0.191, keeping every device safely away from the triode region. All designs also respected the imposed constraints of gm/ID between 5 and 25, phase margin of at least 60 degrees, and power no more than 10 microwatts.

Robustness was then tested against real-world manufacturing reality. Every optimized design was verified with SPICE simulations across the four standard process corners (SS, FF, SF and FS), along with supply and temperature variations. All designs satisfied the target specifications even under worst-case process conditions: gain stayed close to the nominal target, IRN remained well below the required limit, power stayed in the ultra-low-power regime, and phase margin exceeded 79 degrees in all corners, confirming stable operation without any post-design tuning.

The computational economics underline why the approach matters. The team generated a dataset of 3,000 design samples using Cadence Spectre with the TSMC 65-nm CMOS process design kit, automated through MATLAB, which took about 2 hours and 15 minutes on a workstation with an AMD Ryzen processor and 16 GB of RAM. Training the 12-network ensemble took roughly 3.4 minutes, and once trained, the surrogate replaced SPICE during NSGA-II optimization, which completed in about 10.7 minutes for a population of 512 evolved over 400 generations. Because dataset generation and training happen only once, the surrogate can be reused repeatedly for further design exploration. The authors note that migrating to another CMOS technology requires only regenerating the dataset, while the machine-learning framework itself stays unchanged. They also acknowledge limitations: Monte Carlo mismatch analysis, post-layout parasitic extraction and experimental validation through chip fabrication were not included in this study, and are left for future work, along with extending the framework to complete analog front-end architectures.

Subject of Research: Physics-aware deep learning surrogate optimization of low-power OTAs for biosignal acquisition

Article Title: Physics-aware and uncertainty-guided deep learning-based surrogate optimization for low-power OTA design

Article References: Kemie, A. M., & Paily, R. P. (2026). Physics-aware and uncertainty-guided deep learning-based surrogate optimization for low-power OTA design. Discover Electronics, 3(1), Article 144. https://doi.org/10.1007/s44291-026-00277-w

Image Credits: AI Generated

DOI: 10.1007/s44291-026-00277-w

Keywords: OTA, surrogate modeling, deep learning, deep ensembles, uncertainty quantification, NSGA-II, low-power analog design, biosignal acquisition, CCFF amplifier, TSMC 65-nm CMOS, Pareto optimization, gm/ID methodology