In a groundbreaking advancement for three-dimensional (3D) integrated circuit technology, a research team has unveiled an innovative fabrication process that seamlessly integrates pure ruthenium-based nano through-silicon vias (n-TSVs) with an all-dry thinning methodology for silicon-on-insulator (SOI) wafers. This pioneering approach targets the implementation of robust backside power-delivery networks (BSPDNs), crucial for mitigating power routing congestion in sub-3 nanometer technology nodes where traditional copper-based TSVs encounter formidable challenges.
The increasing demand for higher density and performance in integrated circuits has spurred the evolution of 3D architectures, which rely heavily on TSVs for vertical interconnectivity. However, copper—the incumbent material for TSV metallization—faces severe constraints as device dimensions shrink, including limited barrier layer effectiveness, diffusion risks, and oxidation vulnerabilities. To circumvent these limitations, the team focused on ruthenium, a noble metal distinguished by its inherent oxidation resistance and barrier-free compatibility, making it exceptionally suited for high-aspect-ratio nanoscale through-silicon structures.
Central to their technological breakthrough is a meticulously engineered multi-step etching technique leveraging fluorine radicals and oxygen gases. This process enables the fabrication of tapered n-TSV arrays with unprecedented aspect ratios as high as 10.4:1, maintaining critical dimensions down to an extraordinary 39 nanometers. The tapering not only enhances mechanical stability but also ensures superior uniformity and electrical performance across ultra-dense TSV arrays, a necessity for reliable power delivery in advanced 3D ICs.
Following precise silicon etching, the team utilized atomic layer deposition (ALD) to achieve a conformal, void-free deposition of pure ruthenium within the n-TSV cavities. This method effectively eliminates the need for traditional diffusion barrier layers, resulting in an impressive resistivity of 19.9 micro-ohm centimeters for the ruthenium fill—an attribute that underscores the metal’s superior electrical conductivity and reliability under nanoscale confinement.
Innovation extended to post-deposition processing, where a novel dry recess etching protocol based on chlorine and oxygen plasma chemistry was established. This step selectively removes metallic residues from the sidewalls of the TSVs with a ruthenium-to-liner oxide etch selectivity ratio exceeding 50:1. Such precision ensures the integrity of the sidewall dielectric and the elimination of parasitic conductive pathways, which could otherwise compromise device performance and longevity.
Complementing the metallization and etching advances, the researchers implemented an extreme all-dry thinning scheme to prepare SOI wafers. By utilizing the buried oxide layer as a highly reliable etch stop, they achieved wafer thinning down to a top silicon thickness of 500 nanometers, sustaining total thickness variation below 15 nanometers across 200-mm wafers. This rigorous dimensional control is critical for uniform device performance and facilitates the integration of BSPDNs without damaging the delicate TSV structures.
A plasma-assisted all-dry backside reveal technique further exposed the embedded nano TSVs while famously preserving the integrity of the sidewall dielectric liner with less than 1-nanometer loss. This capability offers significant advantages in process control and minimizes potential leakage currents or dielectric breakdown points at the TSV interfaces.
Electrical characterization of the pure ruthenium-filled n-TSVs demonstrated outstanding performance metrics. The average line resistance was measured at 29 ohms per micrometer, indicating exceptional conductivity even at the nanoscale. Reliability tests involving 100 thermal cycles between −40 °C and 125 °C exhibited less than a 1% relative change in resistance, highlighting the robust thermal stability of these interconnects under typical operating environments.
Leakage current assessments reflected similarly encouraging results. Under a 6 V bias, leakage currents remained below 80 picoamperes in dense TSV arrays, and breakdown voltages exceeded 9 V with leakage currents under 0.2 nanoamperes. These findings confirm the dielectric liner’s effectiveness and the TSVs’ ability to withstand high electric fields without degradation or failure.
Notably, accelerated electromigration testing underscored the pure ruthenium n-TSVs’ durability, with time-to-failure metrics consistent with long-term operational stability. This resilience is especially significant as electromigration remains a dominant failure mode in nanoscale metal interconnects, often limiting device lifespan in advanced semiconductor technologies.
Altogether, this integrated process presents a viable and scalable manufacturing pathway for the realization of backside power-delivery networks. By merging novel material selection with precise process engineering—ranging from nano-fabrication to wafer thinning—the approach addresses critical bottlenecks hindering power delivery at sub-3 nm technology nodes, all while paving the way for energy-efficient and high-performance 3D integrated circuits.
This landmark study, titled “Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network,” represents a significant stride in semiconductor innovation, unlocking new horizons for 3D power delivery architectures. The research was conducted by Biao Wang, Feifeng Huang, Qiancheng Wang, Zhao Chen, Hongbin Chen, Quan Wang, Qiu Shao, Yiqin Chen, Zhengyuan Wu, Bo Feng, Ming Ji, and Huigao Duan, and published in the journal Engineering.
For researchers and engineers aiming to transcend the limitations of copper in TSV technologies, this study not only offers a fundamental material innovation but also a comprehensive set of process strategies critical for next-generation semiconductor device fabrication. The all-dry approach minimizes contamination and mechanical stresses, while the ruthenium-based metallization ensures corrosion resistance, electrical reliability, and scalability to the nanoscale dimensions demanded by emerging technology nodes.
The implications of this work stretch beyond just power delivery; integrating such high-aspect-ratio, pure metal TSVs could revolutionize chip stacking and heterogeneous integration, enabling faster, more efficient devices with smaller footprints and lower parasitic losses. As the semiconductor industry relentlessly pursues scaling and performance improvements, adopting such advanced materials and processes will be pivotal in meeting the ever-increasing demands of computing and communication systems.
In summary, this research heralds a promising future for backside power delivery networks, through a synthesis of ruthenium metallization and precise, ultra-thin wafer engineering. Its impact is poised to resonate across the semiconductor landscape, influencing design paradigms and manufacturing protocols alike.
Subject of Research: Advanced nano through-silicon via (n-TSV) fabrication and silicon-on-insulator (SOI) wafer thinning techniques for backside power-delivery network integration in 3D integrated circuits.
Article Title: Pure Ru n-TSV Processing and Extreme All-Dry SOI Wafer Thinning for a Backside Power-Delivery Network
News Publication Date: 4-Apr-2026
Web References:
Full article: https://doi.org/10.1016/j.eng.2025.10.026
Journal website: https://www.sciencedirect.com/journal/engineering
Image Credits: Biao Wang, Feifeng Huang et al.
Keywords
Ruthenium, nano through-silicon vias, TSV, silicon-on-insulator, SOI wafer thinning, backside power-delivery network, 3D integrated circuits, atomic layer deposition, dry etching, high aspect ratio, nanoscale metallization, electromigration.
Tags: 3D integrated circuit technologyadvanced semiconductor manufacturing techniquesall-dry SOI wafer thinningbackside power-delivery networkscopper TSV limitationsfluorine radical etching processhigh-aspect-ratio TSV fabricationnanoscale vertical interconnectsoxidation-resistant TSV materialsruthenium nano through-silicon viassilicon-on-insulator wafer processingsub-3 nanometer technology nodes
