Electronic noise is often the hidden limit in advanced transistor technologies. A device may switch rapidly, consume very little power, and offer an exceptionally steep subthreshold slope, yet still fail in a sensitive circuit if random fluctuations overwhelm the signal. A new study from researchers at Jadavpur University in India examines this challenge in a tunnel field-effect transistor that combines a heterojunction, a double-gate architecture, a p-n-i-n tunneling structure, and a ferroelectric gate layer. The work focuses on how different microscopic noise mechanisms emerge across frequency, temperature, interface conditions, and ferroelectric thickness. Its central message is technologically compelling: carefully engineered ferroelectric gate stacks may not only improve transistor electrostatics, but could also reduce key noise components in future low-power electronics.
The device investigated is a heterojunction double-gate ferroelectric p-n-i-n tunnel field-effect transistor, or HJ DG Fe p-n-i-n TFET. Unlike a conventional metal-oxide-semiconductor transistor, which relies primarily on thermionic emission over an energy barrier, a TFET operates through band-to-band tunneling. When the bands of the source and channel align favorably, carriers can tunnel directly from the valence band on one side of a junction into the conduction band on the other. This mechanism can enable switching at lower supply voltages and potentially produce a subthreshold swing steeper than the conventional 60-millivolt-per-decade limit at room temperature. The heterojunction is used to improve band alignment and tunneling probability, while the double-gate design gives the control terminals stronger influence over the channel potential.
The ferroelectric layer adds another level of electrostatic control. Ferroelectric materials possess a switchable polarization, meaning that their internal electric dipoles can respond to an applied electric field and retain a remanent state. In a transistor gate stack, this polarization can amplify the effective voltage delivered to the semiconductor surface. The resulting voltage amplification may sharpen the transition between the off and on states and enhance the tunneling current without requiring a large external gate voltage. However, ferroelectric materials are not perfectly quiet. Polarization changes, domain-wall motion, defects, and charge trapping can all create fluctuations. Understanding whether the ferroelectric layer ultimately increases or suppresses the total electrical noise therefore requires a detailed analysis rather than a simple comparison of on-state current.
The researchers used technology computer-aided design, or TCAD, simulations to calculate the output current noise power spectral density, designated S_ID, and the input gate-voltage noise power spectral density, designated S_VG. Power spectral density describes how much random fluctuation is present within a narrow frequency interval. S_ID represents current noise observed at the drain, while S_VG expresses the equivalent input voltage fluctuation required to produce the same noise response at the gate. This distinction is important for circuit designers. A transistor can exhibit a modest current-noise level but still have a large equivalent input-voltage noise if its transconductance is weak. Conversely, strong electrostatic control can translate a given current fluctuation into a smaller input-referred disturbance.
The study separates the total noise into three principal components: generation-recombination noise, flicker noise, and diffusion noise. Generation-recombination, or G-R, noise originates from carriers being captured and released by defect states and traps. Because these processes have characteristic time constants, G-R noise is especially influential at very low frequencies, where slow trapping and detrapping events can appear as substantial fluctuations. Flicker noise, commonly called 1/f noise, rises as frequency decreases and is associated with variations in carrier number or mobility. In nanoscale transistors, interface defects and oxide traps can modulate the charge available for conduction, making flicker noise a particularly important concern for analog circuits, sensors, memory elements, and low-frequency signal processing.
At higher frequencies, diffusion noise becomes increasingly prominent. This component is linked to the random motion and statistical arrival of carriers as they cross regions of the device. In a tunneling transistor, the carrier flow is governed by a combination of band alignment, tunneling probability, carrier concentration, and electric-field distribution. As the frequency increases, slower trapping processes contribute less strongly, while faster carrier-transport fluctuations become more visible. The simulated results follow this physically expected progression: G-R noise dominates the very low-frequency regime, flicker noise controls much of the low-to-mid-frequency range, and diffusion-related contributions become more pronounced at high frequencies. The finding provides a useful map for matching device design to circuit application, because different systems operate in very different spectral windows.
Ferroelectric thickness is one of the study’s central design variables. Changing the thickness modifies the capacitance and polarization response of the gate stack, which in turn changes the electric field acting on the tunneling junction. A suitable ferroelectric thickness can improve gate control, strengthen band-to-band tunneling, and reduce the gate voltage needed to achieve a target drain current. These changes can also affect noise because the same electrostatic amplification that improves transconductance may reduce the equivalent input voltage noise. Yet excessive thickness or poorly balanced capacitance can produce undesirable polarization behavior, weaken dynamic response, or make the device more sensitive to internal defects. The simulations therefore treat ferroelectric engineering as a noise-optimization problem rather than merely a current-enhancement strategy.
The analysis also considers donor-type and acceptor-type interface trapped charges. Such charges can alter the local potential near the semiconductor and dielectric boundary, shifting the energy bands and changing the position of the tunneling window. Donor and acceptor traps do not influence the device in identical ways: their charge states can raise or lower the local electrostatic potential, modify carrier concentrations, and affect how efficiently the double gate controls the channel. Since traps are also direct sources of generation-recombination and flicker noise, their impact extends beyond the DC transfer characteristics. The study’s inclusion of both trap polarities highlights a practical reality for ferroelectric electronics: defect engineering, interface passivation, and fabrication quality may be just as important as the nominal properties of the ferroelectric film.
Temperature provides another route through which noise mechanisms change. Thermal energy influences carrier populations, recombination rates, mobility, trap occupancy, and the probability that carriers can access available transport pathways. In tunneling devices, temperature can also modify the balance between direct tunneling and thermally assisted processes. The researchers examined how these changes affect both current-referred and gate-voltage-referred noise. Their work reinforces the idea that a transistor’s noise signature cannot be judged at a single operating point. A structure that performs well at room temperature and moderate frequency may behave differently in cryogenic environments, high-temperature electronics, or circuits that spend long periods near the off-state, where small fluctuations can represent a large fraction of the total signal.
The researchers compare the simulated noise performance of the proposed HJ DG Fe p-n-i-n TFET with several existing TFET designs. The comparison is intended to show how heterojunction tunneling, double-gate electrostatic control, and ferroelectric voltage amplification work together. According to the study, incorporating the ferroelectric material into the gate stack offers a pathway for lowering several noise components while preserving the low-voltage advantages associated with tunnel switching. The authors suggest that this combination could be valuable for high-end analog systems, digital logic, and Internet-of-Things devices, where energy efficiency, sensitivity, and reliable operation must coexist. The implications are especially relevant to edge electronics, which increasingly process weak sensor signals locally rather than sending all raw data to a distant server.
The results should nevertheless be interpreted in the proper context. This is a TCAD-based investigation, not a report of measurements from fabricated devices. Simulations can isolate physical mechanisms and reveal design trends that are difficult to distinguish experimentally, but their predictive power depends on the material parameters, trap models, ferroelectric descriptions, tunneling formulations, and calibration assumptions used. Real devices may introduce additional noise from grain boundaries, domain switching, contact resistance, process variation, aging, random telegraph signals, and nonuniform interface defects. Experimental verification will therefore be essential, particularly across repeated devices and wide temperature and frequency ranges. Even with that qualification, the study offers a valuable framework for designing quieter TFETs. By treating noise as a primary performance metric rather than an afterthought, it points toward ferroelectric transistor architectures capable of combining steep switching, low energy consumption, and improved signal integrity in the next generation of intelligent electronics.
Subject of Research: Noise characteristics of a heterojunction double-gate ferroelectric p-n-i-n tunnel field-effect transistor
Article Title: Evaluation of electronic noise components in heterojunction double gate ferroelectric p-n-i-n tunnel field-effect transistors
Article References: Das, S. S., & Sarkar, S. K. “Evaluation of electronic noise components in heterojunction double gate ferroelectric p-n-i-n tunnel field-effect transistors.” Applied Nanoscience, 16, Article 5 (2026). Published 18 December 2025.
Image Credits: AI Generated
DOI: 10.1007/s13204-025-03134-6
Keywords: Ferroelectric TFET, G-R noise, flicker noise, diffusion noise, power spectral density, interface trapped charges, tunnel field-effect transistor, TCAD simulation, low-frequency noise, ferroelectric gate stack
Tags: advanced tunnel transistor architecturesdouble-gate heterojunction TFETselectronic noise in tunnel FETsferroelectric gate layer effectsferroelectric tunnel transistorsfrequency and temperature dependence of electronic noiseimpact of ferroelectric thickness on device performanceinfluence of ferroelectric stacks on electrostaticsinterface conditions in tunnel FETslow-power transistor noise analysismicroscopic noise mechanisms in transistorsnoise reduction strategies for low-power electronics
