For nearly two decades, the landscape of semiconductor technology has been captivated by the promise of two-dimensional (2D) materials as a transformative alternative to conventional silicon transistors. These atomically thin semiconductors have intrigued researchers worldwide, heralded for their potential to drive the next generation of processors that are not only smaller in size but also demonstrate markedly enhanced speed and energy efficiency. Yet, despite the intense focus and optimistic projections, a fundamental challenge has persisted: how to evaluate the true performance capabilities of 2D transistors in a manner that aligns with practical, commercial technology constraints.
A team of electrical engineers at Duke University, led by Professor Aaron Franklin—an established figure in nanotechnology and semiconductor research—has recently shed critical light on this issue. The researchers uncovered that a widely used testing framework, known popularly as the “back-gated” architecture, inherently distorts the functional metrics of 2D-based transistors due to an effect called “contact gating.” This architectural nuance, they revealed, amplifies transistor performance in experimental setups but fails to translate into viable commercial devices, raising important questions about the reliability of past performance benchmarks across the field.
Traditionally, back-gated transistor devices are constructed with all components layered on a single silicon wafer, employing the substrate itself as a gate electrode to control current flow through the ultrathin 2D semiconductor channel—often single layers of materials like molybdenum disulfide (MoS₂). Although this configuration simplifies fabrication and experimentation, it fundamentally couples the gate voltage not only to the active semiconductor channel but also to the semiconductor region beneath the metal contacts. This coupling induces “contact gating,” wherein the gate modulates the interface between metal contacts and the 2D semiconductor, artificially lowering contact resistance and thus enhancing current flow in ways that would not naturally occur in isolated, realistic technological implementations.
Contact gating, while seemingly advantageous due to the boost in transistor drive current and switching speeds, introduces artifacts that complicate fair assessment of the semiconductor’s intrinsic qualities. Professor Franklin emphasizes that such performance gains, manifest in these back-gated testbeds, cannot be straightforwardly scaled into commercial technology platforms. Speed limitations and current leakage inherent to this approach fundamentally limit its practical utility, meaning that reported “high-performance” metrics in the extensive literature may not reflect genuine advances achievable in downscaled device architectures aligned with industrial standards.
To quantify and contextualize the impact of contact gating, graduate student Victoria Ravel and her colleagues undertook a breakthrough experimental initiative. They engineered a carefully designed symmetric dual-gate transistor architecture, which incorporates independent gates both above and below a monolayer 2D semiconductor channel. This design allowed for precise modulation of the semiconductor channel either with or without the contact gating mechanism, enabling a direct, apples-to-apples comparison that isolates the contact gating effect from other device variables.
Fabricating these nanoscale devices presented formidable technical challenges, as process control at the scale of just a few atoms demands meticulous precision and innovative fabrication strategies. Despite these obstacles, Ravel succeeded in producing functional devices and systematically varying their dimensions, offering unprecedented empirical insights into the interplay between device scaling and contact gating impact.
The experimental results were striking. In devices with relatively larger channel lengths, the presence of contact gating roughly doubled transistor performance. However, as the device dimensions shrank into the regime relevant for future technology nodes—sub-50-nanometer channel lengths with ultra-short contact lengths of approximately 30 nanometers—the contact gating effect became dramatically more pronounced. At these scales, contact gating was observed to amplify performance by as much as six times, a profound inflation of transistor capabilities attributed solely to architectural influence rather than intrinsic material improvements.
This scaling dependence arises because, in nanoscale transistors, metal-semiconductor contacts increasingly dominate overall device behavior. Consequently, any gate-induced modulation of contacts disproportionately affects transport characteristics and device effectiveness. This insight fundamentally challenges prior assumptions and underscores the necessity of re-evaluating past data collected chiefly on back-gated devices to ensure realistic projections as 2D materials advance toward integration in commercial chip manufacturing.
Looking forward, the Duke team intends to push the envelope even further by fabricating transistors with contact lengths scaled down to 15 nanometers—the tantalizing frontier approaching ultimate device miniaturization limits. They also plan to explore alternative contact metal materials designed to reduce contact resistance without relying on contact gating, a critical step towards defining clear design rules for incorporating 2D semiconductors into next-generation transistor technologies.
The implications of these findings are far-reaching. If 2D materials are to displace silicon as the foundational channel material in future processors, a clear and honest understanding of how device architecture affects experimental measurements is essential. The work spearheaded by Franklin and Ravel establishes a necessary foundation to ensure that performance metrics are truly indicative of physical material properties rather than experimental artifacts, guiding the field toward realistic and reproducible transistor designs.
This research represents a pivotal advancement in materials science and nanoscale electronics, merging fundamental physics with practical engineering considerations. The study also highlights the importance of rigorous experimental design and the critical examination of semi-empirical fabrication methods before scaling emerging materials into commercial technology—a cautionary tale for researchers excited by the tantalizing promises of next-generation semiconductors.
Supported by the National Science Foundation, this study was recently published in the prestigious journal ACS Nano and is set to influence the trajectory of 2D semiconductor research and integration strategies for years to come. As the race to extend Moore’s Law continues, understanding the intricate subtleties of contact gating in 2D devices will be crucial in turning laboratory breakthroughs into industrial realities.
Subject of Research: Not applicable
Article Title: Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure
News Publication Date: 17-Feb-2026
Web References: DOI: 10.1021/acsnano.5c19797
References:
Ravel, V. M., Evans, S. R., Holmes, S. K., Doherty, J. L., Rahman, M. S., Roy, T., & Franklin, A. D. (2026). Impact of Contact Gating on Scaling of Monolayer 2D Transistors Using a Symmetric Dual-Gate Structure. ACS Nano. DOI: 10.1021/acsnano.5c19797
Keywords
2D semiconductors, transistor scaling, contact gating, molybdenum disulfide, dual-gate architecture, nanoscale transistors, device fabrication, contact resistance, transistor performance, Moore’s Law, energy-efficient processors, nanotechnology
Tags: 2D semiconductor transistor performanceAaron Franklin nanotechnologyadvanced transistor benchmarking issuesback-gated transistor architecturecommercial viability of 2D transistorscontact gating effect in transistorsDuke University transistor researchnanotechnology in semiconductor processorsnext-generation transistor lab testsoverstated transistor metricspractical constraints in transistor testingsemiconductor device evaluation challenges
