In the relentless pursuit of transcending the physical limitations imposed by silicon-based semiconductor technology, researchers have increasingly turned their gaze toward two-dimensional (2D) materials. Characterized by atomic-scale thickness and excellent carrier mobility, these materials promise to revolutionize the field of microelectronics by delivering unprecedented scaling opportunities and enhanced performance metrics. A recent breakthrough, reported by Ghosh et al. in Nature, marks a transformative milestone in this domain, presenting the first functional complementary metal–oxide–semiconductor (CMOS) one instruction set computer (OISC) constructed entirely from 2D materials. This development not only showcases the potential of 2D semiconductors for next-generation devices but also redefines the pathway toward practical integration of these materials in complex circuits.
Silicon’s dominance in the semiconductor industry is underpinned by decades of technological refinement centered around miniaturization, yet inevitable scaling challenges—ranging from short-channel effects to heat dissipation—have spurred the search for novel materials and architectures. Two-dimensional materials such as molybdenum disulfide (MoS₂) and tungsten diselenide (WSe₂) offer compelling advantages, including atomically thin channels ideal for electrostatic control and high carrier mobilities that surpass silicon in certain contexts. Yet, integrating these materials into complementary logic circuits, essential for power-efficient and high-performance digital electronics, has remained a significant hurdle, primarily due to difficulties in wafer-scale synthesis, doping control, and contact engineering.
Addressing these challenges head-on, the team engineered a CMOS platform by heterogeneously integrating large-area n-type MoS₂ and p-type WSe₂ field-effect transistors (FETs). This heterogeneous approach leverages the unique electronic properties of each material, enabling effective complementary operation. To optimize device performance, careful scaling of channel length and the adoption of a high-κ gate dielectric material were implemented. These design strategies were crucial for tailoring threshold voltages across both n-type and p-type transistors, ensuring that the devices operate efficiently and minimize leakage currents, which are detrimental to power consumption and overall circuit stability.
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A key achievement of this research lies in the demonstration of robust device characteristics at scaled dimensions. Through precise material growth protocols and meticulous postprocessing techniques, the researchers attained transistor configurations that deliver high drive currents while suppressing subthreshold leakage. This balance is vital since the drive current dictates the switching speed and processing capability, whereas leakage currents impact power efficiency—a central consideration for any scalable semiconductor technology aiming to compete with established silicon processes.
The integrated 2D CMOS circuits exhibited functional operation below 3 volts, a testament to the meticulous engineering of device interfaces and gating architectures. The realized circuits achieved switching frequencies reaching up to 25 kHz, an impressive figure constrained predominantly by parasitic capacitances inherent in the device layout and fabrication processes. Although this frequency lags behind silicon microprocessors, it represents a pioneering proof of concept that validates the viability of 2D materials in practical computational hardware.
Noteworthy is the remarkably low power consumption observed in the 2D OISC system, operating in the picowatt range, coupled with energy-per-switching-event as low as approximately 100 picojoules. Such ultra-low power characteristics are highly desirable for applications demanding energy efficiency, including wearable electronics, implantable biomedical devices, and ubiquitous sensor networks. In these contexts, the ability to perform computations without significant power overhead could enable a new class of persistent, autonomous systems.
The authors did not stop at experimental demonstration. They further developed a comprehensive SPICE-compatible BSIM-BULK model calibrated with empirical device data, including variability across multiple transistor samples. By incorporating these realistic device-to-device variations, the modeling efforts provided invaluable insights into the scalability and practical performance bounds of the 2D material-based CMOS circuits. When benchmarked against state-of-the-art silicon microelectronics, the projections suggest that while current performance does not yet rival traditional silicon solutions, continuous material and processing improvements could close this gap, heralding a new era of 2D electronics.
This study epitomizes the complex interplay between advanced materials synthesis, device physics, and circuit design. Achieving complementary operation with two distinct 2D semiconductors required overcoming numerous technical barriers, including uniform wafer-scale crystal growth, controllable doping levels, and the formation of low-resistance, thermally stable contacts. The successful co-integration of n-type MoS₂ and p-type WSe₂ FETs on a common substrate signals a critical step toward scalable manufacturing processes compatible with existing silicon fab infrastructure.
From a broader perspective, this advance invites a reevaluation of long-standing paradigms in semiconductor technology, particularly as industry demands increasingly push beyond silicon’s fundamental limits. The ability to engineer and integrate atomically thin materials at wafer scale opens exciting frontiers not only for logic electronics but also for optoelectronics, flexible devices, and sensors. The modularity of 2D materials offers tantalizing prospects for heterogeneous integration with other emerging platforms, potentially fostering hybrid architectures that leverage the best attributes of multiple material systems.
Importantly, the research highlights the practical significance of device variability and interface engineering in 2D electronics. The authors’ approach in modeling and benchmarking accounts for real-world nonidealities, which is essential to translating lab-scale breakthroughs into industrial applications. Furthermore, the adopted high-κ gate dielectric, alongside efforts in threshold voltage tuning, illustrates how traditional semiconductor engineering principles must be adapted and refined for atomically thin materials.
The prototype one instruction set computer implemented in this work embodies a minimalist yet fully functional computing architecture, which, despite its simplicity, demonstrates the essential building blocks of digital logic implemented through 2D semiconductor technology. Its successful operation at ultra-low voltages and power levels underscores the inherent advantages of 2D materials for energy-efficient electronics while serving as a scalable platform for more complex integrated circuits.
While significant challenges remain —including improving operating frequency, enhancing device uniformity, and integrating with complementary fabrication techniques—the demonstrated system forms a pivotal foundation for future explorations in 2D microelectronics. It sparks optimism within the scientific community, signifying that 2D material-based complementary circuits may soon transition from academic curiosities to practical technologies integrated into everyday electronic devices.
In summation, the work by Ghosh and colleagues not only affirms the potential of 2D materials as viable alternatives to silicon in CMOS logic but also represents a landmark in the field’s evolution. By successfully synthesizing, engineering, and integrating large-area MoS₂ and WSe₂ transistors into a functional computing architecture, they have illuminated a promising path forward for the semiconductor industry. With continued research and development, the vision of ultra-scaled, energy-efficient 2D material-based microprocessors may well materialize, radically reshaping the landscape of electronics.
Subject of Research: Complementary CMOS circuits based on two-dimensional n-type MoS₂ and p-type WSe₂ field-effect transistors for logic computing.
Article Title: A complementary two-dimensional material-based one instruction set computer.
Article References:
Ghosh, S., Zheng, Y., Rafiq, M. et al. A complementary two-dimensional material-based one instruction set computer. Nature 642, 327–335 (2025). https://doi.org/10.1038/s41586-025-08963-7
Image Credits: AI Generated
DOI: https://doi.org/10.1038/s41586-025-08963-7
Tags: 2D materials in electronicsatomically thin semiconductor materialsbreakthroughs in microelectronicscomplementary metal-oxide-semiconductor technologyhigh-performance digital circuitsintegration of 2D semiconductorsmicroelectronics innovationmolybdenum disulfide applicationsone instruction set computerscaling challenges in technologysilicon semiconductor alternativestungsten diselenide properties