Researchers at the National University of Singapore have developed a reconfigurable transistor that can filter image data before it reaches an artificial-intelligence network while also serving as a building block for the network itself. In simulations based on measurements of the device, the resulting system reduced the number of active computing tiles needed to recognise handwritten digits by about 36%, with accuracy falling by only 0.3 percentage points. A separate traffic-scene model estimated larger energy savings when the system isolated a vehicle or its number plate.
The experimental study, published in Nature Electronics on 14 September 2026, demonstrates an approach in which hardware can be allocated according to the visual information required by a task. The work addresses a mismatch between visual-recognition tasks and the hardware used to perform them. A neural network may need to inspect only a small, relevant part of a scene, yet conventional hardware often converts and processes the complete image.
As cameras capture increasingly detailed images, surrounding pixels can trigger computational activity even when those details contribute little to the final result. That unnecessary activity consumes energy, a concern for battery-powered security cameras, drones and other edge devices that must analyse visual information while keeping power use low. The researchers’ architecture places configurable logic circuits ahead of a spiking neural network so that unwanted pixels can be blocked before they generate neural activity.
At the centre of the system is a “spiking neural network-in-logic” arrangement, named for the division of work between its two components. Rule-based logic circuits receive control signals specifying which image regions should be retained. They pass the selected pixels onward while preventing the rest from reaching the neural network.
Only the retained information is converted into spikes, the brief electrical pulses used to communicate within the spiking network. In this sense, the arrangement performs selective attention: it identifies potentially useful information, discards unneeded data and then engages the more computationally intensive network. The device does not determine that every visually irrelevant detail can safely be removed.
The simulations instead show that the amount of filtering must match the features required by the particular task. Making this possible at the device level required the same transistors to perform two different jobs. Logic filtering depends on reliable switching, whereas a neural-network device must combine temporary responses with stored information.
Those requirements are usually met with disparate device structures. The NUS researchers engineered the material layers and electrical controls of one transistor so that it could supply all three behaviours. They assembled the devices into small units called tiles and allowed each tile to be assigned either to image filtering or to neural-network calculations.
When the filtering stage removes unnecessary data, fewer tiles need to operate within the network, directly reducing the active hardware required to process the image. The transistor carries current through an atomically thin layer of molybdenum disulfide, or MoS₂, a two-dimensional semiconductor. Two gates control the current.
One incorporates hafnium zirconium oxide, a ferroelectric material in which voltage can alter the alignment of positive and negative charges. The duration of voltage pulses applied to this gate determines whether the device produces a temporary or lasting response to an electrical signal. Brief pulses generate effects that build up and then fade, allowing the transistor to mimic the transient behaviour of a neuron.
Longer pulses retain electrical charge and create a lasting change in current flow. That change can store a synaptic weight, representing the strength of a connection within the network. Under steady voltages, the same transistor can perform logic operations needed to filter visual information.
The team grew the atomically thin MoS₂ using metal-organic chemical vapour deposition in its laboratory and fabricated the transistors through processes described as compatible with mainstream chip manufacturing. According to co-author Lance Li, the material exhibited high quality and strong uniformity across the wafer. He said this combination is critical because practical AI hardware and other large-scale integrated applications require many devices to perform consistently.
The research team also had to reconcile two competing demands: preserving reliable switching for logic while allowing some electrical signals to persist and others to fade. Ang Kah-Wee said the engineers studied the interfaces between material layers and used that understanding to design both the transistor and the electrical signals that controlled it. To test whether the architecture could recognise images with fewer active tiles, the researchers ran simulations informed by measurements of their transistors.
They compared recognition from complete 28-by-28-pixel handwritten-digit images with results obtained after cropping the images to 20 by 20 pixels. Cropping lowered the total number of active tiles by about 36%, even after including the tiles needed for filtering. The number of synaptic weights stored in the network fell by almost half.
Accuracy was 95.9% for the full-image baseline and declined by only 0.3 percentage points under the 20-by-20-pixel condition. More aggressive cropping was not equally useful: at 16 by 16 pixels, portions of the digits were cut away and accuracy dropped to 94.4%. The comparison shows that useful filtering depends on retaining the visual features required for a specific recognition task.
The researchers next modelled a traffic scene to estimate how the architecture might perform across tasks with different spatial requirements. Identifying a vehicle requires a broader view of its shape, whereas reading a number plate depends on a smaller area containing finer detail. In a simulation using a 3,072-pixel traffic image, selecting the vehicle region reduced estimated energy consumption by about 59% compared with processing the complete image.
Selecting the smaller number-plate region produced a further reduction, bringing the estimated saving to about 77%. The simulations also indicated that the energy advantage grew as image resolution increased. These figures are model estimates rather than measurements from a complete working chip.
They cover the computing arrays and exclude supporting circuits, so they do not represent total system-level energy use. The next stage is to develop AI accelerator chiplets that combine the energy-conscious computing architecture with new memory technologies and high-speed connections that transfer data using light. The researchers plan to test these components on realistic AI workloads and assess energy efficiency, latency and data movement across an entire system.
That work would move the concept beyond device measurements and simulations toward evaluation of how performance and energy trade-offs translate into integrated hardware. Possible visual applications include autonomous vehicles, drones and smart cameras, which must interpret large amounts of sensor data quickly while keeping power consumption low. The study establishes the reconfigurable device and task-dependent filtering architecture, while broader benefits will depend on successful chiplet integration and validation in operational systems.
Subject of Research: Reconfigurable transistors for filtering visual data before spiking neural-network processing
Article Title: NUS CDE researchers design AI hardware that filters out irrelevant visual data
Article References: NUS CDE researchers design AI hardware that filters out irrelevant visual data. Original publication (Bibliographic details unavailable.)
Image Credits: AI Generated
DOI: Not provided
Keywords: reconfigurable transistors, spiking neural networks, edge AI, visual data filtering, molybdenum disulfide, ferroelectric gating, energy-efficient computing, AI accelerators, selective attention, handwritten-digit recognition, researchers, design
News Source: Denise Maddox. (October 21, 2026). Research report: NUS CDE researchers design AI hardware that filters out irrelevant visual data. Scienmag.
