FPGA and ASIC designs accelerate CORDIC with carry-lookahead adders

A high-speed hardware architecture for generating sine and cosine values combines the Coordinate Rotation Digital Computer (CORDIC) algorithm with carry-lookahead adders, delivering improved computational speed over conventional ripple-carry implementations. Researchers synthesized the design on both an FPGA and a standard-cell ASIC, reporting accurate trigonometric outputs, low power consumption and successful timing closure in the tested configurations.

The architecture uses a pipelined, scale-free CORDIC datapath. Carry-lookahead adders are incorporated into timing-critical stages to shorten critical-path delay, while hybrid configurations retain ripple-carry adders in less critical paths. The study presents this selective arrangement as a way to balance computational performance against hardware cost rather than using the faster adder type throughout the entire circuit.

The design also employs mutually exclusive micro-rotation techniques. According to the researchers, these techniques reduce the number of CORDIC iterations and eliminate the need for scale-factor compensation. Together with the pipelined datapath and hybrid adder arrangement, these changes are intended to improve the efficiency of hardware-based sine and cosine generation.

FPGA implementation on a Xilinx Artix-7 device confirmed accurate sine and cosine outputs at a reported power consumption of 0.175 W. The authors also evaluated a standard-cell ASIC implementation using the open SkyWater 130 nm process design kit and the Yosys–OpenROAD flow. This version achieved a core area of 0.88 mm², an achievable clock frequency of 32 MHz and total power consumption of 10.2 mW.

The ASIC design completed timing closure with zero violations across all sign-off corners, providing evidence that the proposed architecture can be implemented beyond FPGA prototyping. The reported results are tied to the specific FPGA, process technology and synthesis flow used in the study, so they describe the tested implementations rather than universal performance across other hardware platforms.

Subject of Research: FPGA and ASIC hardware acceleration of CORDIC-based trigonometric signal generation

Article Title: High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders

Article References: Kanadal, K. M., Pradhan, A. K., S, A., & Roy, C. (2026). High-speed FPGA implementation of the CORDIC algorithm using carry lookahead adders. Scientific Reports. https://doi.org/10.1038/s41598-026-74995-2

Image Credits: AI Generated

DOI: 10.1038/s41598-026-74995-2

Keywords: CORDIC algorithm, FPGA, ASIC design, carry-lookahead adder, trigonometric generation, hardware acceleration, pipelined architecture, SkyWater 130 nm, Yosys, OpenROAD, High-speed, implementation