Quantum-Dot Memory Cells Shrink to the Nanoscale in New QCA Design

For decades, the engine of the digital revolution has been the relentless shrinking of the transistor. But as silicon devices approach atomic dimensions, the industry is confronting a hard physical wall: transistors can no longer be made smaller without leaking current, dissipating heat, and losing reliability. A new study published in Scientific Reports by Priyanka Wani and Sankit Kassa of Symbiosis Institute of Technology in Pune, India, offers a glimpse of what might come after the transistor era. The researchers have designed and verified two remarkably compact memory circuits based on quantum-dot cellular automata, a computing paradigm that abandons the flow of electric current altogether and encodes information instead in the position of single electrons within nanoscale cells.

Quantum-dot cellular automata, or QCA, is one of the most actively explored alternatives to complementary metal–oxide–semiconductor technology, the CMOS framework that underpins virtually every chip manufactured today. In a QCA circuit, the basic unit is a square cell containing four quantum dots, with two mobile electrons that tend to occupy diagonally opposite dots. Because there are two possible diagonal arrangements, each cell can represent a binary one or a binary zero. Information propagates not through wires carrying current but through Coulombic interactions: the electron configuration of one cell influences its neighbor, and arrays of cells can be arranged to perform logic operations. The result is a technology that promises switching speeds in the terahertz range, feature sizes at the molecular scale, and power consumption orders of magnitude below conventional electronics.

The centerpiece of the new work is a D-latch, a fundamental building block of digital memory that holds a single bit of data as long as an enable signal remains active. Latches are the precursors to flip-flops and registers, and any practical QCA-based processor would need thousands of them. Wani and Kassa’s design uses a majority-feedback architecture, exploiting the majority gate that serves as the native logic primitive of QCA. A majority gate outputs the value held by the majority of its three inputs, and by feeding the output back into one of the inputs, the circuit can hold its state indefinitely, which is precisely the behavior required of a latch. The elegance of this approach lies in its economy: instead of assembling latches from many separate logic gates, the feedback structure folds the storage function into a small cluster of cells.

The numbers reported in the study are striking. The optimized D-latch requires only 14 QCA cells arranged in a single layer and occupies a footprint of just 0.007 square micrometers. Single-layer designs are particularly valuable because multi-layer QCA fabrication, which stacks cells above one another, remains one of the most difficult manufacturing challenges facing the technology. By keeping everything on one plane, the researchers sidestep a major engineering bottleneck. Compared with a similar latch previously reported in the literature, the new circuit reduces the layout area, the latency, and the overall QCA cost, a composite metric that combines cell count, wire crossings, and the area consumed by the design.

Latency matters as much as area in memory design. In QCA, information ripples through the cell array one clock zone at a time, so the number of clock zones a signal must traverse determines how quickly the circuit responds. Each clocking zone in a QCA layout is driven by a four-phase clock that pumps information forward, and every additional zone adds delay and switching energy. By carefully arranging cells to minimize the critical path, the researchers produced a latch that settles to its stored value with fewer clock cycles than competing designs. For memory arrays, where read and write operations occur billions of times per second, such savings compound into significant gains in throughput and efficiency.

The second contribution of the paper addresses a practical requirement of real memory systems: the ability to deliberately overwrite stored data. The researchers extended their latch into a 15-cell variant equipped with SET and RESET control signals, making it suitable for use as a static random-access memory cell. In conventional SRAM, each bit is stored in a cross-coupled pair of inverters that can be written and read through access transistors. The QCA equivalent achieves the same function through its majority-feedback structure, with the SET and RESET inputs allowing the cell to be forced into a known state regardless of what was previously stored. This control capability is essential for initializing memory, clearing registers, and implementing the write operations that random-access memory demands.

Power analysis revealed another advantage of the SET/RESET-enabled design. Using QCAPro, a simulation tool that models the thermodynamic behavior of QCA circuits, the researchers mapped the energy dissipation and polarization characteristics of both circuits. The 15-cell memory cell was found to reduce peak energy dissipation by approximately 22 percent relative to the 14-cell baseline latch. This counterintuitive result, in which an additional cell yields lower peak power, reflects the way control signals can steer the circuit through lower-energy switching paths. In a technology whose central promise is ultra-low power consumption, trimming energy at the level of individual memory cells is a meaningful step toward practical nanoelectronic systems.

All designs were implemented and functionally verified in QCADesigner version 2.0.3, the standard simulation environment for QCA research. Functional verification confirms that the circuits produce the correct logical outputs across their input space, while the power and polarization analyses in QCAPro provide a window into the physical behavior of the electrons within each cell. This combination of logic-level and energy-level simulation is the accepted methodology in the QCA community for evaluating whether a proposed circuit is not only logically correct but also physically plausible and energy-efficient. The study reports that both circuits performed as intended, validating the majority-feedback approach as a reliable template for memory elements.

The significance of this work extends beyond the specific circuits described. Memory is one of the most demanding tests of any candidate post-CMOS technology, because practical systems require enormous arrays of identical, reliable, low-power storage elements. Demonstrating a latch and an SRAM cell with minimal cell counts, single-layer layouts, and quantified energy savings provides a concrete data point in the ongoing comparison between QCA and incumbent technologies. If QCA is ever to move from simulation to fabrication at scale, designs like these, which minimize the number of cells and avoid multi-layer complexity, will define the benchmarks that manufacturing processes must meet.

Considerable challenges remain before quantum-dot cellular automata can challenge silicon in commercial products. Fabricating and clocking arrays of quantum dots with the required precision, maintaining coherence at room temperature, and integrating millions of cells are problems that no laboratory has yet solved. But each incremental improvement in circuit density, latency, and power efficiency brings the field closer to viability. Wani and Kassa’s optimized latch and memory cell, published as open-access research with a permanent DOI, add to a growing library of compact QCA primitives that future designers can assemble into larger systems. As CMOS scaling slows, such foundational work on alternative computing substrates may prove to be among the most consequential research of the coming decade.

Subject of Research: Quantum-dot cellular automata memory circuit design for nanoelectronics

Article Title: An optimized majority-feedback QCA D-latch and SET/RESET-enabled SRAM cell for compact, low-latency nanoelectronic memory design

Article References: Wani, P., & Kassa, S. (2026). An optimized majority-feedback QCA D-latch and SET/RESET-enabled SRAM cell for compact, low-latency nanoelectronic memory design. Scientific Reports. https://doi.org/10.1038/s41598-026-74675-1

Image Credits: AI Generated

DOI: 10.1038/s41598-026-74675-1

Keywords: quantum-dot cellular automata, QCA, nanoelectronics, SRAM, D-latch, memory design, power dissipation, latency, CMOS, majority gate, QCADesigner, QCAPro