A new physics-guided artificial intelligence framework could change how engineers design one of the most important circuits inside modern wireless devices. Researchers from the Singapore University of Technology and Design, Tianjin University and Henan University of Technology have developed an automated method for optimizing 2.4 GHz CMOS low-noise amplifiers, or LNAs, while dramatically reducing power consumption, improving signal linearity and avoiding the high failure rate that has traditionally made AI-assisted circuit design difficult. In simulations using a commercial 40-nanometer CMOS process, the method reduced power use by 62 percent and improved linearity by 10.7 decibels compared with an expert-designed reference circuit.
LNAs are small but essential components found in smartphones, Wi-Fi routers, wearable electronics and other radio-frequency systems. Their job is to amplify extremely weak signals received by an antenna before those signals pass to later stages of a wireless receiver. Because the incoming signal may be only slightly stronger than background noise, an LNA must provide substantial gain without adding too much noise of its own. At the same time, it must remain sufficiently linear so that strong nearby signals do not distort the information being received. These demands compete with one another, and lowering power consumption adds another layer of difficulty. A circuit that performs well in one category can easily compromise another.
Designing such an amplifier traditionally requires extensive experience with radio-frequency electronics, semiconductor manufacturing rules and circuit simulation. Engineers adjust transistor dimensions, bias conditions, matching networks and passive components through repeated rounds of testing. Each change can affect noise figure, gain, stability, power consumption and linearity in ways that are difficult to predict. The process can take days of manual iteration, particularly when designers must work within a foundry’s process design kit, or PDK. A PDK defines which transistors, capacitors, resistors and inductors can actually be manufactured, as well as the electrical limits those devices must satisfy.
Artificial intelligence appears to offer a faster alternative, but conventional optimization algorithms often struggle with the realities of analog circuit design. Many algorithms generate candidate circuits by exploring a broad mathematical design space, even when large parts of that space are physically impossible or incompatible with the manufacturing process. In the researchers’ preliminary experiments, more than half of the simulated designs failed. Some violated transistor operating conditions, while others could not satisfy impedance-matching requirements or used component combinations unavailable in the PDK. Every failed simulation consumed computing time without producing useful information for the optimization model.
The new framework addresses this problem by giving the algorithm basic physical knowledge before the search begins. Instead of generating candidates randomly, it uses relationships involving resonance, impedance matching and radio-frequency circuit behavior to create an initial group of designs that are more likely to be functional and manufacturable. These “warm-start” candidates are assembled using components from the foundry’s approved library. The approach does not attempt to replace detailed circuit simulation with simplified equations. Rather, it uses those equations to guide the first stage of exploration toward regions of the design space where valid amplifiers are more likely to exist.
The system then combines a validity gate with multi-objective Bayesian optimization. Bayesian optimization is designed for problems in which each evaluation is expensive, as is the case with transistor-level circuit simulation. After observing the performance of previously tested designs, the algorithm builds a statistical model that estimates how new candidates are likely to perform. It then selects the next candidates by balancing exploration of unfamiliar designs with exploitation of designs that already appear promising. In this study, the algorithm simultaneously considered several competing objectives, including power consumption, noise figure and input third-order intercept point, or IIP3, a widely used measure of linearity.
The validity gate acts as a protective filter between the optimizer and the simulation results. Candidates that fail basic physical or process-aware checks are identified and prevented from misleading the statistical model. Only meaningful simulation outcomes are used to guide later decisions. This distinction is important because a failed circuit is not simply a poor-performing circuit; it may provide no reliable information about the trade-offs among power, noise and linearity. By excluding invalid results from the learning process, the framework can concentrate its limited simulation budget on designs that can actually be compared.
The researchers tested the approach on a 2.4 GHz LNA implemented in a commercial 40 nm CMOS technology. Within a budget of 190 circuit simulations, requiring approximately 16 to 19 hours of computing, the optimized design reduced power consumption from 14.1 milliwatts for the handcrafted reference to 5.4 milliwatts. That represents a 62 percent reduction, a significant improvement for battery-powered devices and densely integrated wireless systems. The circuit also delivered a 10.7 dB improvement in IIP3, indicating substantially better resistance to distortion from strong signals. The main trade-off was a modest 0.21 dB increase in noise figure, a relatively small penalty compared with the gains in power and linearity.
The effect of physics-guided initialization and validity screening was equally striking. Under unguided sampling, only 47.5 percent of the simulated candidates were valid. With the new method, the valid-simulation rate rose to 95.7 percent. The researchers report that this was roughly twice the rate achieved by popular open-source optimizers operating under the same simulation budget. In practical terms, the improvement means that almost every simulation contributes useful information instead of being lost to an impossible circuit. That efficiency could make automated optimization more attractive for analog and radio-frequency design, where each high-fidelity simulation can be computationally expensive.
To determine whether the method depended too heavily on one particular amplifier structure, the team applied the same pipeline to a structurally different LNA without retuning the optimization strategy. The second experiment again surpassed the expert-designed baseline. Power consumption fell by 25 percent, the noise figure improved by 0.36 dB and linearity increased by 2.59 dB. The result suggests that the framework may capture a reusable design strategy rather than merely exploiting quirks in a single circuit topology. However, the researchers emphasize that the work remains a schematic-level proof of concept. Real-world chip development will require additional testing after layout, including parasitic effects, process-voltage-temperature corners and possible interactions with neighboring circuits. Future versions could be applied to power amplifiers, mixers, oscillators and other RF blocks. If the method continues to perform under those more demanding conditions, physics-aware AI could become a practical design assistant for the analog circuits that connect electronic devices to the wireless world.
Subject of Research: CMOS low-noise amplifier design and physics-guided multi-objective Bayesian optimization
Article Title: Physics-guided multi-objective Bayesian optimization for process-aware CMOS LNA design
News Publication Date: 30-Jul-2026
Web References: https://doi.org/10.55092/interdiscipline20260002
References: Jayarajan J, Ji S, Thangarasu B, Mahalingam N, Miao B, et al. “Physics-guided multi-objective Bayesian optimization for process-aware CMOS LNA design.” Interdiscipline, 2026(1):0002. DOI: 10.55092/interdiscipline20260002
Image Credits: Jithish Jayarajan/Singapore University of Technology and Design; Kiat Seng Yeo/Singapore University of Technology and Design, Tianjin University; Shuoyu Ji, Bharatha Kumar Thangarasu, Nagarajan Mahalingam/Tianjin University; Baoji Miao/Henan University of Technology
Keywords
Artificial intelligence, Bayesian optimization, CMOS, low-noise amplifier, LNA, radio-frequency circuits, analog circuit design, semiconductor engineering, wireless technology, circuit simulation, physics-guided AI, multi-objective optimization
Tags: advanced semiconductor process simulationsAI-assisted RF circuit optimizationautomated circuit design methodsCMOS 2.4 GHz LNA designfailure rate reduction in AI circuit designlow-noise amplifier power reductionlow-noise amplifiers in smartphones and Wi-Finoise reduction in RF amplifiersphysics-guided AI for circuit optimizationpower-efficient wireless receiver componentssignal linearity improvement in LNAswireless device circuit design
